Semiconductor device structures including stair step structures, and related semiconductor devices

• US 10,672,657 B2
• Filed: 02/27/2018
• Issued: 06/02/2020
• Est. Priority Date: 08/27/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Park, Matthew, Olson, Adam L., Yu, Jixin
• Primary Examiner(s): Mazumder, Didarul A
• Application Number:
  US15/906,366
• Publication Number:
  US 20180190587A1
• Time in Patent Office: 826 Days
• Field of Search: 257773, 438618, 438666
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.

Claims

1. A semiconductor device structure, comprising:

a stair step structure comprising steps at least partially defined by laterally peripheral portions of partially conductive tiers overlying a substrate, the steps comprising;

a lower step;

an upper step; and

a middle step longitudinally between the lower step and the upper step, the middle step having a greater width than a width of the lower step and a width of the upper step; and

non-uniformly spaced contact structures over and in contact with the steps.

2. The semiconductor device structure of claim 1, wherein the steps further comprises a lowermost step located most longitudinally proximate the substrate and having a width greater than the lower step.

3. A semiconductor device, comprising:

alternating conductive structures and insulating structures arranged in stacked tiers overlying a substrate, each of the stacked tiers comprising one of the conductive structures and one of the insulating structures;

a stair step structure comprising steps comprising lateral end portions of the stacked tiers, the steps comprising;

a first step;

a second step longitudinally above the first step and having a larger width than the first step; and

a third step longitudinally above the second step and having a smaller width than the second step; and

contact structures in physical contact with the steps.

4. The semiconductor device of claim 3, wherein each of the steps exhibits a different width than each other of the steps.

5. The semiconductor device of claim 3, wherein at least some of the steps exhibit a first width and at least some other of the steps exhibit a second width larger than the first width.

6. The semiconductor device of claim 5, wherein the at least some steps are located more proximate the substrate than the at least some other of the steps.

7. The semiconductor device of claim 3, wherein the contact structures are non-evenly spaced apart from one another.

8. The semiconductor device of claim 3, wherein:

the first step is directly laterally adjacent the second step; and

the second step is directly laterally adjacent the third step.

9. The semiconductor device of claim 3, further comprising a fourth step having a larger width than the third step.

10. The semiconductor device of claim 9, wherein the fourth step is longitudinally farther from the substrate than the third step.

11. The semiconductor device of claim 3, further comprising at least one additional step having the same width as one of the first step, the second step, and the third step.

12. A semiconductor device, comprising:

a conductive stack structure comprising tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the conductive structure;

a stair step structure having steps comprising lateral ends of the tiers of the conductive stack structure, at least four of the steps having different widths than one another, and the steps comprising;

a step;

another step; and

at least one additional step longitudinally between the step and the another step, the at least one additional step having a greater width than each of the step and the another step; and

conductive contact structures in physical contact with the steps of the stair step structure.

13. The semiconductor device of claim 12, wherein each of the steps of the stair step structure has a different width than each other of the steps of the stair step structure.

14. The semiconductor device of claim 12, wherein at least one of the steps of the stair step structure has the same width as at least one other of the steps of the stair step structure.

15. The semiconductor device of claim 12, wherein each of the conductive contact structures is centrally laterally positioned on a step of the stair step structure.