Nonvolatile memory device having a vertical structure and a memory system including the same

• US 10,672,791 B2
• Filed: 11/27/2018
• Issued: 06/02/2020
• Est. Priority Date: 11/27/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lim, Bong-soon, Kim, Jin-young, Shim, Sang-won, Park, Il-han
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US16/200,714
• Publication Number:
  US 20190164991A1
• Time in Patent Office: 553 Days
• Field of Search: 36518512, 365 63, 36518511, 36518505
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

Claims

1. A nonvolatile memory device, comprising:

a first semiconductor layer comprising a first upper substrate and a second upper substrate adjacent to each other in a first direction and a memory cell array that comprises a plurality of memory blocks arranged in a second direction and first and second vertical structures, the first vertical structure comprising a plurality of first gate conductive layers stacked on the first upper substrate and a plurality of first pillars that pass through the first gate conductive layers and extend in a third direction perpendicular to the first and second directions, the second vertical structure comprising a plurality of second gate conductive layers stacked on the second upper substrate and a plurality of second pillars that pass through the second gate conductive layers and extend in the third direction; and

a second semiconductor layer located under the first semiconductor layer in the third direction, wherein the second semiconductor layer comprises a lower substrate that comprises a plurality of row decoder circuits and a plurality of page buffer circuits,

wherein the first vertical structure further comprises a first via area in which a first through-hole via passes through the first vertical structure and is connected to a first page buffer circuit, and a first partial block spaced apart from the first via area in the second direction, and

the second vertical structure further comprises a second via area in which a second through-hole via passes through the second vertical structure and is connected to a second page buffer circuit, and a second partial block spaced apart from the second via area in the second direction.

2. The nonvolatile memory device of claim 1, wherein the first partial block overlaps the second via area in the first direction, and

the second partial block overlaps the first via area in the first direction.

3. The nonvolatile memory device of claim 1, wherein the second semiconductor layer comprises first, second, third and fourth regions that are divided along the first and second directions, wherein at least one of the first, second, third and fourth regions overlaps the memory cell array,

wherein the first page buffer circuit is located in the first region and a second page buffer circuit is located in the third region.

4. The nonvolatile memory device of claim 3, wherein the plurality of row decoder circuits comprise first and second row decoder circuits respectively located in the second and fourth regions,

wherein the second partial block is electrically connected to the first row decoder circuit, and the first partial block is electrically connected to the second row decoder circuit.

5. The nonvolatile memory device of claim 4, further comprising a control circuit configured to control the first and second row decoder circuits to simultaneously access the first partial block and the second partial block.

6. The nonvolatile memory device of claim 4, further comprising a control circuit configured to control the first and second row decoder circuits to independently access the first partial block and the second partial block.

7. The nonvolatile memory device of claim 1, wherein the first partial block comprises a plurality of strings each comprising a plurality of memory cells stacked from the first upper substrate in the third direction.

8. The nonvolatile memory device of claim 1, wherein the first partial block comprises a third through-hole via that passes through the plurality of first gate conductive layers in the third direction.

9. The nonvolatile memory device of claim 8, wherein the second semiconductor layer further comprises a peripheral circuit electrically connected to the third through-hole via.

10. The nonvolatile memory device of claim 1, wherein the first partial block is provided plural in number, and

the second partial block is provided plural in number,

wherein the number of the first partial blocks and the number of the second partial blocks are equal to each other.