Stacked gate all around MOSFET with symmetric inner spacer formed via sacrificial pure Si anchors

• US 10,672,891 B2
• Filed: 10/04/2018
• Issued: 06/02/2020
• Est. Priority Date: 10/04/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hashemi, Pouya, Ando, Takashi, Lee, Choonghyun, Zhang, Jingyun
• Primary Examiner(s): Smith, Zandra V
• Assistant Examiner(s): Tynes, Jr., Lawrence C
• Application Number:
  US16/152,022
• Publication Number:
  US 20200111888A1
• Time in Patent Office: 607 Days
• Field of Search: None
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31105 Etching inorganic layers
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of forming a stacked gate all around MOSFET is provided. A stack of alternating layers of Si and SiGe are formed on a substrate. A number of holes are etched through the stack and Si anchors formed in the holes. The SiGe layers are removed. A number of dummy gates are formed on the substrate and a Low-K spacer material deposited around the dummy gates. A number of S/D recesses are etched through the Si layers, removing the Si anchors. The dummy gates and spacer material preserves sections of the Si layers during etching, forming stacks of Si channels. S/Ds are formed in the recesses. The dummy gates are then removed replaced with metal gate stacks.

Claims

1. A method of forming a stacked gate all around MOSFET, comprising steps of:

stacking a number of semiconductor layers on a substrate, wherein the stacked layers alternate between a primary semiconductor material and a sacrificial semiconductor material;

etching a number of holes through the stacked layers;

forming anchors in the holes, wherein the anchors comprise the primary semiconductor material;

removing the sacrificial semiconductor material;

forming a number of dummy gates on the substrate;

depositing a layer of spacer material around the dummy gates;

etching a number of source/drain (S/D) recesses through the layers of primary semiconductor material and removing the anchors, wherein the dummy gates and spacer material preserve semiconductor channels from among the layers of primary semiconductor material during etching of the S/D recesses;

forming S/Ds in the S/D recesses;

removing the dummy gates, leaving spaces; and

forming metal gates in the spaces left by the dummy gates.

2. The method of claim 1, wherein the primary semiconductor material is Si.

3. The method of claim 1, wherein the sacrificial semiconductor material is SiGe.

4. The method of claim 1, wherein the spacer material comprises SiBCN.

5. The method of claim 1, wherein the dummy gates comprise HSQ.

6. The method of claim 1, further comprising depositing a dielectric over the S/Ds.

7. The method of claim 6, further comprising:

etching back the dielectric from the top of the spacer material around the dummy gates to form an etch recess; and

depositing a Low-K dielectric layer in the etch recess before removal of the dummy gates.

8. The method of claim 1, further comprising depositing a layer of High-K dielectric within the spaces left by the dummy gates before forming the metal gates.

9. The method of claim 1, wherein the S/Ds are grown epitaxially.

10. A method of forming a stacked gate all around MOSFET, comprising steps of:

forming a stack of a number of alternating layers of Si and SiGe on a substrate;

etching a number of holes through the stack;

forming Si anchors in the holes;

removing the SiGe layers;

forming a number of dummy gates on the substrate;

depositing a Low-K spacer material around the dummy gates;

etching a number of source/drain (S/D) recesses through the Si layers and removing the Si anchors, wherein the dummy gates and spacer material preserves sections of the Si layers during etching of the S/D recesses, forming stacks of Si channels;

forming S/Ds in the S/D recesses; and

removing the dummy gates and replacing them with metal gates.

11. The method of claim 10, further comprising depositing a High-K layer inside spaces left by the dummy gates before forming the metal gate stacks.

12. The method of claim 10, wherein the dummy gates comprise HSQ.

13. The method of claim 10, wherein the spacer material comprises SiBCN.

14. The method of claim 10, further comprising depositing a dielectric over the S/Ds.

15. The method of claim 14, further comprising:

etching back the dielectric from the top of the spacer material around the dummy gates to form an etch recess; and

depositing a Low-K dielectric layer in the etch recess before removal of the dummy gates.

16. The method of claim 10, wherein the S/Ds are grown epitaxially.

17. A stacked gate all around MOSFET, comprising:

a substrate;

a number of stacked Si channels over the substrate;

a metal gate surrounding the stacked Si channels;

a spacer surrounding the metal gate stack;

a source/drain (S/D) on opposite ends of the stacked Si channels; and

a Si pad protruding from the substrate into a bottom surface of each S/D.

18. The MOSFET of claim 17, further comprising a High-K dielectric layer between the metal gate and spacer.

19. The MOSFET of claim 17, wherein the S/D comprises P or As doped Si or Si:

C.

20. The MOSFET of claim 17, wherein the S/D comprises B doped Si or SiGe.