Microfabricated ultrasonic transducers and related apparatus and methods

• US 10,672,974 B2
• Filed: 10/12/2018
• Issued: 06/02/2020
• Est. Priority Date: 03/08/2017
• Status: Active Grant

• Current Assignee: BFLY Operations, Inc. (Butterfly Network, Inc.)
• Original Assignee: Butterfly Network, Inc.
• Inventors: Rothberg, Jonathan M., Alie, Susan A., Fife, Keith G., Sanchez, Nevada J., Ralston, Tyler S., Zahorian, Jaime Scott
• Primary Examiner(s): Lopez, Feifei Yeung
• Application Number:
  US16/158,999
• Publication Number:
  US 20190047850A1
• Time in Patent Office: 599 Days
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: B06B 1/0622 on one surface
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 2201/038 Microengines and actuators not provided for in B81B2201/031 - B81B2201/037
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: B81C 1/00182 Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 2201/013 Etching
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H10N 30/01 Manufacture or treatment

Abstract

Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

Claims

1. A method of fabricating an ultrasound device, the method comprising:

forming, in a first wafer having a first silicon device layer and a dielectric layer, a plurality of cavities by completely etching through a first thickness of the dielectric layer and by partially etching through a second thickness of the first silicon device layer, wherein at least one of the plurality of cavities comprises an inner cavity portion and an outer cavity portion that at least partially surrounds the inner cavity portion, the outer cavity portion having a greater depth than the inner cavity portion, and wherein forming the plurality of cavities comprises forming the outer cavity portion by completely etching through the first thickness of the dielectric layer and by partially etching through the second thickness of the first silicon device layer and forming the inner cavity portion by completely etching through the first thickness of the dielectric layer until at least a portion of the first silicon device layer is uncovered; and

bonding a second wafer, having a second silicon device layer, with the first wafer so that the plurality of cavities are disposed between the first silicon device layer and the second silicon device layer.

2. The method of claim 1, wherein bonding the second wafer with the first wafer comprises annealing the bonded first and second wafers at a temperature greater than 500°

C.

3. The method of claim 1, wherein bonding the second wafer with the first wafer comprises forming a Si—

SiO₂ bond or a SiO₂—

SiO₂ bond.

4. The method of claim 1, further comprising thinning a portion of the second silicon device layer.

5. The method of claim 1, further comprising bonding a CMOS wafer with the bonded first and second wafers at a temperature that is less than 450°

C.

6. The method of claim 5, further comprising placing a bonding material in contact with the second silicon device layer, and wherein bonding the CMOS wafer with the bonded first and second wafers comprises placing a metallization layer of the CMOS wafer electrically in contact with the bonding material.

7. The method of claim 1, wherein the first wafer is a silicon-on-insulator (SOI) wafer and the second wafer is a bulk silicon wafer.

8. The method of claim 1, wherein the outer cavity portion has a width that is between 100 nm and 500 μ

m.

9. The method of claim 8, wherein the inner cavity portion has a width that is less than 400 μ

m.

10. The method of claim 1, further comprising forming a passivation layer to cover the plurality of cavities.