Single carrier-based data transmission method and apparatus

• US 10,673,677 B2
• Filed: 11/02/2018
• Issued: 06/02/2020
• Est. Priority Date: 05/06/2016
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Wu, Tao
• Primary Examiner(s): Qureshi, Afsar M
• Application Number:
  US16/179,449
• Publication Number:
  US 20190075008A1
• Time in Patent Office: 578 Days
• CPC Class Codes: H04L 1/0058 Block-coded modulation
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 27/361 Modulation using a single or unspecified number of carriers, e.g. with separate stages of phase and amplitude modulation
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits

Abstract

Embodiments of the present disclosure describe a single carrier-based data transmission method and apparatus. The method may include generating a frame and sending the frame. A data part of the frame includes 2N data blocks, the 2N data blocks are arranged in a sequence from the first data block to the 2N^th data block. Furthermore, the data block includes a payload part and a guard interval (GI), payload parts of different data blocks are separated by GIs, and a payload part of the 2N^th data block is obtained by multiplying a payload part of the (2n−1)^th data block by a phase-shift sequence, where n=1, 2, . . . , N, and N is an integer greater than 0. By using the foregoing manner, data transmission robustness can be improved and data transmission for a longer distance can be supported.

Claims

1. A single carrier-based data transmission method, wherein the method comprises:

generating a frame, wherein a data part of the frame comprises 2N data blocks, the 2N data blocks are arranged in a sequence from a first data block to a 2N^th data block, each data block comprises a payload part and a guard interval (GI), payload parts of different data blocks are separated by GIs, and a payload part of a 2n^th data block is obtained by multiplying a payload part of a (2n−

1)^th data block by a phase-shift sequence, wherein n=1, 2, . . . , N, and N is an integer greater than 0; and

sending the frame.

2. The method according to claim 1, wherein a phase-shift coefficient of the phase-shift sequence is stipulated in a standard, and the phase-shift coefficient comprises:

90°

, 180°

, or 270°

.

3. The method according to claim 1, wherein a signaling part of the frame comprises a phase field, and the phase field comprises 1 bit, wherein:

when the phase field is a first value, a phase-shift coefficient of the phase-shift sequence is 0°

;

or when the phase field is a second value, a phase-shift coefficient of the phase-shift sequence is 180°

.

4. The method according to claim 1, wherein a signaling part of the frame comprises a phase field, and the phase field comprises at least 2 bits, wherein:

when the phase field is a first value, a phase-shift coefficient of the phase-shift sequence is 0°

;

when the phase field is a second value, a phase-shift coefficient of the phase-shift sequence is 90°

;

when the phase field is a third value, a phase-shift coefficient of the phase-shift sequence is 180°

;

or when the phase field is a fourth value, a phase-shift coefficient of the phase-shift sequence is 270°

.

5. The method according to claim 3, wherein before the generating a frame, the method further comprises:

receiving channel feedback information, wherein the channel feedback information comprises the phase-shift coefficient.

6. The method according to claim 1, wherein a payload part of a data block comprises 448 symbols, and a guard interval of a data block comprises 64 symbols.

7. A single carrier-based data transmission apparatus, wherein the apparatus comprises:

a baseband processor configured to generate a frame, wherein a data part of the frame comprises 2N data blocks, the 2N data blocks are arranged in a sequence from a first data block to a 2N^th data block, each data block comprises a payload part and a guard interval (GI), payload parts of different data blocks are separated by GIs, and a payload part of a 2n^th data block is obtained by multiplying a payload part of a (2n−

1)^th data block by a phase-shift sequence, wherein n=1, 2, . . . , N, and N is an integer greater than 0; and

a transceiver configured to send the frame.

8. The apparatus according to claim 7, wherein a phase-shift coefficient of the phase-shift sequence is stipulated in a standard, and the phase-shift coefficient comprises:

90°

, 180°

, or 270°

.

9. The apparatus according to claim 7, wherein a signaling part of the frame generated by the baseband processor comprises a phase field, and the phase field comprises 1 bit, wherein:

when the phase field is a first value, a phase-shift coefficient of the phase-shift sequence is 0°

;

or when the phase field is a second value, a phase-shift coefficient of the phase-shift sequence is 180°

.

10. The apparatus according to claim 7, wherein a signaling part of the frame generated by the baseband processor comprises a phase field, and the phase field comprises at least 2 bits, wherein:

when the phase field is a first value, a phase-shift coefficient of the phase-shift sequence is 0°

;

when the phase field is a second value, a phase-shift coefficient of the phase-shift sequence is 90°

;

when the phase field is a third value, a phase-shift coefficient of the phase-shift sequence is 180°

;

or when the phase field is a fourth value, a phase-shift coefficient of the phase-shift sequence is 270°

.

11. The apparatus according to claim 9, wherein before the baseband processor generates the frame, the transceiver is further configured to receive channel feedback information, wherein the channel feedback information comprises the phase-shift coefficient.

12. The apparatus according to claim 7, wherein a payload part of a data block comprises 448 symbols, and a guard interval of a data block comprises 64 symbols.

13. A non-transitory computer readable medium storing computer executable instructions that when executed by a processor instruct the processor to:

generate a frame, wherein a data part of the frame comprises 2N data blocks, the 2N data blocks are arranged in a sequence from a first data block to a 2N^th data block, each data block comprises a payload part and a guard interval (GI), payload parts of different data blocks are separated by GIs, and a payload part of a 2n^th data block is obtained by multiplying a payload part of a (2n−

1)^th data block by a phase-shift sequence, wherein n=1, 2, . . . , N, and N is an integer greater than 0; and

send the frame.

14. The non-transitory computer readable medium of claim 13, wherein a phase-shift coefficient of the phase-shift sequence is stipulated in a standard, and the phase-shift coefficient comprises:

90°

, 180°

, or 270°

.

15. The non-transitory computer readable medium of claim 13, wherein a signaling part of the frame comprises a phase field, and the phase field comprises 1 bit, wherein:

when the phase field is a first value, a phase-shift coefficient of the phase-shift sequence is 0°

;

or when the phase field is a second value, a phase-shift coefficient of the phase-shift sequence is 180°

.

16. The non-transitory computer readable medium of claim 13, wherein a signaling part of the frame comprises a phase field, and the phase field comprises at least 2 bits, wherein:

when the phase field is a first value, a phase-shift coefficient of the phase-shift sequence is 0°

;

when the phase field is a second value, a phase-shift coefficient of the phase-shift sequence is 90°

;

when the phase field is a third value, a phase-shift coefficient of the phase-shift sequence is 180°

;

or when the phase field is a fourth value, a phase-shift coefficient of the phase-shift sequence is 270°

.

17. The non-transitory computer readable medium of claim 15, wherein before generating the frame, computer executable instructions when executed by the processor further instruct the processor to receive channel feedback information, wherein the channel feedback information comprises the phase-shift coefficient.

18. The non-transitory computer readable medium of claim 13, wherein a payload part of a data block comprises 448 symbols, and a guard interval of a data block comprises 64 symbols.