Non-deterministic memory protocol

• US 10,678,441 B2
• Filed: 08/28/2018
• Issued: 06/09/2020
• Est. Priority Date: 05/05/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Walker, Robert M., Hall, Jr., James A., Ross, Frank F.
• Primary Examiner(s): Ruiz, Aracelis
• Application Number:
  US16/115,004
• Publication Number:
  US 20180364910A1
• Time in Patent Office: 651 Days
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1626 by reordering requests
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.

Claims

1. An apparatus, comprising:

a memory device including a non-volatile memory array and a volatile memory array; and

a controller, coupled to the memory device, configured to;

receive a first command requesting data from the memory device followed by a second command requesting data from the memory device;

send a first read ready signal to a host in response to the data associated with the second command being located in the volatile memory array;

send a second read ready signal to the host in response to the data associated with the first command being located in the non-volatile memory array;

execute the second command according to a protocol; and

execute the first command after executing the second command according to the protocol.

2. The apparatus of claim 1, wherein the memory device is a non-volatile dual in-line memory module (NVDIMM) device.

3. The apparatus of claim 1, wherein the protocol provides the host direct access to the memory device.

4. The apparatus of claim 1, wherein the protocol includes the memory device executing operations in an order that is different than an order in which the commands are received by the memory device.

5. The apparatus of claim 1, wherein the protocol includes executing commands associated with data in the volatile memory array before executing command associated with data in the non-volatile memory array.

6. The apparatus of claim 1, wherein the controller can include a write buffer and a read buffer.

7. An apparatus comprising:

a memory device; and

a controller, coupled to the memory device, configured to;

receive a first read command from a host;

receiving a second read command from the host after receiving the first read command;

send a first read ready signal to the host in response to the controller having data associated with the second read command ready to send to the host; and

send a second read ready signal to the host in response to the controller having data associated with the first read command ready to send to the host.

8. The apparatus of claim 7, wherein the controller is configured to receive a first read send signal from the host in response to the host receiving the first read ready signal from the controller, wherein the host can send the first read send signal any time the host is ready to receive the data associated with the second read command.

9. The apparatus of claim 8, wherein the controller is configured to send the data associated with the second read command and a first read identification (RID) signal to the host on a data bus in response to receiving the first read send signal.

10. The apparatus of claim 7, wherein the controller is configured to receive the first read command and the second read command without timing delays between the first read command and the second read command.

11. The apparatus of claim 7, wherein the controller is configured to receive a second read send signal from the host in response to the host receiving the second read ready signal from the controller and to send the data associated with the first read command and a second RID signal to the host on the data bus in response to receiving the second read send signal.

12. The apparatus of claim 11, wherein the host can send the second read send signal to control data traffic on the data bus.

13. The apparatus of claim 11, wherein the host can send the second read send signal after the host has received data associated with another command sent to another memory device by the host after the first read command and the second read command were sent to the controller by the host.

14. An apparatus, comprising:

a memory device; and

a controller, coupled to the memory device, configured to;

receive a first write command from a host;

receive a first read command from the host;

send a first read ready signal to the host prior to executing the first write command in response to the controller having data associated with the first read command ready to send to the host.

15. The apparatus of claim 14, wherein the controller is configured to:

receive data associated with the first write command from the host on a data bus after a first write data transfer time period associated with the first write command; and

send a first write count increment signal to the host in response to writing the data associated with the first write command.

16. The apparatus of claim 15, wherein the first write count increment signal is sent to the host in response to writing the data associated with the first write command being retired from a write buffer in the memory device.

17. The apparatus of claim 15, wherein the first write count increment signal is used by to the host to determine an amount of write commands available to send to the controller.

18. The apparatus of claim 15, wherein the controller is configured to receive a second write command from the host after the first write data transfer time period associated with the first write command.

19. The apparatus of claim 18, wherein the controller is configured to receive data associated with the second write command from the host on the data bus after a second write data transfer time period associated with the second write command.

20. The apparatus of claim 14, wherein the controller is configured to receive a second read command from the host after receiving the first write command and to send a second ready signal to the host in response to the controller having data associated with the second read command ready to send to the host.