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Holdup self-tests for power loss operations on memory systems

  • US 10,678,667 B1
  • Filed: 12/21/2018
  • Issued: 06/09/2020
  • Est. Priority Date: 12/21/2018
  • Status: Active Grant
First Claim
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1. A system comprising:

  • a holdup circuit to provide holdup energy to the system for a set of power loss operations by the system;

    a memory component operatively coupled with the holdup circuit; and

    a processing device, operatively coupled with the memory component and the holdup circuit, to;

    receive a first request to perform a holdup self-test in a self-test mode of the system;

    identify a memory location of the memory component that is available to write self-test data during the self-test mode responsive to the first request;

    detect a loss of power to the system while in the self-test mode;

    responsive to detection of the loss of power, perform a continuous sequence of write operations to write the self-test data to the memory location using the holdup energy from the holdup circuit until an amount of holdup energy is expended;

    after reboot of the system, determine a number of write operations successfully completed in the memory location by the continuous sequence of write operations before the amount of holdup energy is expended;

    determine whether the number of write operations successfully completed satisfies a defect criterion; and

    responsive to the number of write operations successfully completed satisfying the defect criterion, report a defect associated with the holdup circuit.

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