Holdup self-tests for power loss operations on memory systems

• US 10,678,667 B1
• Filed: 12/21/2018
• Issued: 06/09/2020
• Est. Priority Date: 12/21/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Majerus, Douglas, Byron, Brent
• Primary Examiner(s): Chaudry, Mujtaba M
• Application Number:
  US16/231,081
• Publication Number:
  US 20200201730A1
• Time in Patent Office: 536 Days
• Field of Search: None
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

Described herein are embodiments related to holdup self-tests in memory sub-systems for power loss operations. A processing device receives a request to perform a holdup self-test to detect a defect in a holdup circuit that powers the processing device and a memory component in the event of power loss. The processing device identifies a memory location of memory that is available and, responsive to detection of a loss of power, performs a continuous sequence of write operations to the memory location using holdup energy until all of the holdup energy is expended. After reboot, the processing device determines a number of the write operations that were successfully completed in the memory location before all of the holdup energy was expended. The processing device determines whether the number satisfies a defect criterion. Responsive to the responsive to the number satisfying the defect criterion, the processing device reports the defect associated with the holdup circuit.

Claims

1. A system comprising:

a holdup circuit to provide holdup energy to the system for a set of power loss operations by the system;

a memory component operatively coupled with the holdup circuit; and

a processing device, operatively coupled with the memory component and the holdup circuit, to;

receive a first request to perform a holdup self-test in a self-test mode of the system;

identify a memory location of the memory component that is available to write self-test data during the self-test mode responsive to the first request;

detect a loss of power to the system while in the self-test mode;

responsive to detection of the loss of power, perform a continuous sequence of write operations to write the self-test data to the memory location using the holdup energy from the holdup circuit until an amount of holdup energy is expended;

after reboot of the system, determine a number of write operations successfully completed in the memory location by the continuous sequence of write operations before the amount of holdup energy is expended;

determine whether the number of write operations successfully completed satisfies a defect criterion; and

responsive to the number of write operations successfully completed satisfying the defect criterion, report a defect associated with the holdup circuit.

2. The system of claim 1, wherein the holdup circuit comprises:

an array of capacitors to store holdup energy, wherein the array of capacitors has an expected energy capacity; and

an energy transfer circuit to transfer the holdup energy stored in the array of capacitors to the processing device and the memory component responsive to the loss of power, wherein the number of write operations successfully completed represents an actual capacity of the array of capacitors, wherein the defect criterion defines a minimum number of write operations needed to perform the set of power loss operations, wherein the minimum number of write operations represents an expected minimum capacity of the array of capacitors, wherein the defect is detected responsive to the number of write operations successfully completed being less than the minimum number of write operations corresponding to the expected minimum capacity.

3. The system of claim 1, wherein the memory component is a disk, wherein the holdup circuit comprises:

an energy transfer circuit to transfer the holdup energy created from the disk spinning before the loss of power to the processing device and the memory component responsive to the loss of power,

wherein the number of write operations successfully completed represents an actual capacity of the holdup circuit, wherein the defect criterion defines a minimum number of write operations needed to perform the set of power loss operations, wherein the minimum number of write operations represents an expected minimum capacity created from the disk spinning, wherein the defect is detected responsive to the number of write operations successfully completed being less than the minimum number of write operations corresponding to the expected minimum capacity.

4. The system of claim 1, wherein the defect is at least one of an open capacitor in an array of capacitors of the holdup circuit, a malfunctioning cell of a battery of the holdup circuit, an improper resistor setting in the holdup circuit, or an improper function by the holdup circuit comprising a storage chip and a holdup energy source.

5. The system of claim 1, wherein the holdup circuit comprises:

a holdup energy source selectively coupled to the processing device and the memory component responsive to the loss of power; and

a storage chip operatively coupled to an external power source, the holdup energy source, the processing device, and the memory component, wherein the storage chip is to detect the loss of power from the external power source, send an interrupt to the processing device, and selectively couple the holdup energy source to the processing device and the memory component responsive to the loss of power from the external power source.

6. The system of claim 1, wherein the holdup circuit comprises:

a power manager circuit coupled between an external power source and the processing device and the memory component; and

a holdup energy source selectively coupled to the processing device, the memory component, and the power manager circuit, wherein the power manager circuit is configured to de-couple the external power source from the processing device and the memory component to cause the loss of power to the system while in the self-test mode.

7. The system of claim 1, wherein the processing device, to detect the loss of power, is to receive an interrupt indicating the loss of power, wherein the defect criterion corresponds to a holdup requirement for the holdup circuit.

8. The system of claim 1, wherein the processing device is to receive the first request from a test device during manufacturing of the system.

9. The system of claim 1, wherein the processing device is to receive the first request from a host device coupled to the system.

10. The system of claim 1, wherein the processing device, responsive to the first request, is to transition to a state in which the continuous sequence of write operations begins upon detection of a next power loss event and in which, after the reboot of the system, the self-test data is read from the memory location and compared to control data to determine the number of write operations successfully completed before the amount of holdup energy is expended.

11. The system of claim 1, further comprising a second memory component operatively coupled to the processing device and the holdup circuit, wherein the processing device is further to:

identify a second memory location of the second memory component that is available to write the self-test data responsive to the first request;

responsive to the loss of power, perform the continuous sequence of write operations to write the self-test data to the memory location and the second memory location using the holdup energy from the holdup circuit until the amount of holdup energy is expended; and

after reboot of the system, determine the number of the write operations successfully completed in the memory location and the second memory location, wherein the continuous sequence of write operations to write the self-test data to the memory location and the second memory location is at least a part of a write pattern that emulates actual power loss operations performed during a loss of power to the system while not in the self-test mode.

12. The system of claim 1, wherein the processing device is further to:

erase the self-test data written to the memory location; and

report results of the holdup self-test, wherein the results include the defect associated with the holdup circuit responsive to the number of write operations successfully completed satisfying the defect criterion.

13. The system of claim 1, wherein the processing device is further to:

send a second request to a host device, coupled to the system, to disconnect the system from an external power source while the system is in the self-test mode; and

subsequent to the second request, detect the loss of power to the system while in the self-test mode.

14. A storage system comprising:

a power manager circuit to supply power from an external power source or a secondary power source;

a plurality of memory components coupled to the power manager circuit; and

a controller coupled to the power manager circuit and the plurality of memory components, wherein the controller, in response to a request, is to;

identify a set of available blocks in the plurality of memory components, wherein the set of available blocks comprises an available block in each of the plurality of memory components;

detect a power loss condition in which power from the external power source is lost;

responsive to detection of the power loss condition, continuously write test data in the set of available blocks in a specified pattern until an amount of power from the secondary power source is expended by supplying power to the controller and the plurality of memory components during the power loss condition;

responsive to restoration of the power from the external power source, read written data results from the set of available blocks and determine whether the secondary power source has a defect using at least the written data results; and

responsive to detection of the defect, report the defect of the secondary power source.

15. The storage system of claim 14, wherein the controller, to determine whether the secondary power source has the defect, is to:

identify the set of available blocks in which the test data is continuously written;

compare the written data results read from the set of available blocks with control data to determine a number of write operations successfully completed before the amount of power from the secondary power source is expended;

determine whether the number of write operations successfully completed satisfies a defect criterion, wherein the defect criterion corresponds to a minimum energy capacity needed to perform a set of power loss operations to comply with a holdup requirement; and

responsive to the number of write operations successfully completed satisfying the defect criterion, report that the secondary power source has the defect; and

responsive to the number not satisfying the defect criterion, report that the secondary power source does not have the defect.

16. The storage system of claim 14, wherein the secondary power source comprises an array of capacitors, and wherein the defect is at least one of an open capacitor in the array of capacitors.

17. A method comprising:

receiving, by a controller, a request to transition to a holdup self-test mode to check for a defect in a secondary power source of a memory system comprising the controller and a plurality of memory components;

responsive to the request, identifying a set of available memory locations in the plurality of memory components;

detecting a power loss condition of the memory system in which power supplied by a primary power source to the memory system is removed;

responsive to detection of the power loss condition, supplying power to the memory system via a secondary power source;

responsive to detection of the power loss condition, writing a specified pattern of test data in the set of available memory locations until an amount of power from the secondary power source is expended;

responsive to restoration of the power to the memory system by the primary power source, determining whether the secondary power source has a defect using results of the specified pattern of test data written in the set of available memory locations before the amount of power from the secondary power is expended; and

reporting that the secondary power source has the defect responsive to a determination that the secondary power source has the defect.

18. The method of claim 17, wherein the determining whether the secondary power source has the defect comprises:

reading written data results from the set of available memory locations;

comparing the written data results with control data;

determining a number of write operations successfully completed before the amount of power from the secondary power source is expended;

determining whether the number of write operations successfully completed satisfies a defect criterion; and

responsive to the number of write operations successfully completed satisfying the defect criterion, reporting that the secondary power source has the defect; and

responsive to the number not satisfying the defect criterion, reporting that the secondary power source does not have the defect.

19. The method of claim 17, wherein the receiving the request comprises receiving the request from a host device coupled to the memory system, wherein the reporting that the secondary power source has the defect comprises sending a response to the host device, the response comprising an indication of the defect.

20. The method of claim 17, wherein the detecting the power loss condition of the memory system comprises receiving an interrupt indicating a loss of power.