Apparatus for connecting non-volatile memory locally to a GPU through a local switch

• US 10,678,733 B2
• Filed: 04/10/2019
• Issued: 06/09/2020
• Est. Priority Date: 12/23/2016
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Osqueizadeh, Nima
• Primary Examiner(s): Martinez, David E
• Application Number:
  US16/380,005
• Publication Number:
  US 20190243791A1
• Time in Patent Office: 426 Days
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

Described herein are a method and device for transferring data in a computer system. The device includes a host processor, a plurality of first memory architectures, a switch, a redundant array of independent drives (RAID) assist unit; and a second memory architecture. The host processor is configured to send a data transfer command to the RAID assist unit via the switch. The RAID assist unit is configured to create a set of parallel memory transactions between the plurality of first memory architectures and the second memory architecture, execute the set of parallel memory transactions via the local switch and absent interaction with the host processor; and notify the host processor upon completion of data transfer. In an implementation, the plurality of first memory architectures is non-volatile memories (NVMs) and the second memory architecture is local memory.

Claims

1. A method for transferring data in a computer system comprising:

receiving, at a redundant array of independent drives (RAID) assist unit, a data transfer command from a host processor via a switch;

creating, by the RAID assist unit, a set of parallel memory transactions between a plurality of first memory architectures and a second memory architecture, wherein the RAID assist unit is connected to each of the plurality of first memory architecture units and the switch;

segmenting and distributing, by the RAID assist unit, the set of parallel memory transactions amongst the plurality of first memory architecture units via the switch and absent interaction with the host processor; and

notifying, by the RAID assist unit, the host processor upon completion of data transfer.

2. The method of claim 1, further comprising:

writing the data transfer command into a submission queue in the RAID assist unit.

3. The method of claim 2, further comprising:

writing an entry to a register in the RAID assist unit to initiate creation of the set of parallel memory transactions.

4. The method of claim 3, further comprising:

writing a completion entry in a completion queue in the RAID assist unit upon completion of the data transfer.

5. The method of claim 1, wherein the plurality of first memory architectures is non-volatile memories (NVMs) and the second memory architecture is local memory.

6. A device comprising:

a host processor;

a plurality of first memory architectures;

a switch;

a redundant array of independent drives (RAID) assist unit; and

a second memory architecture;

wherein the host processor is configured to send a data transfer command to the RAID assist unit via the switch;

wherein the RAID assist unit is configured to;

create a set of parallel memory transactions between the plurality of first memory architectures and the second memory architecture, wherein the RAID assist unit is connected to each of the plurality of first memory architecture units and the switch;

segment and distribute the set of parallel memory transactions amongst the plurality of the first memory architecture units via the switch and absent interaction with the host processor; and

notify the host processor upon completion of data transfer.

7. The device of claim 6, wherein the host processor is further configured to write the data transfer command into a submission queue in the RAID assist unit.

8. The device of claim 7, wherein the host processor is further configured to write an entry to a register in the RAID assist unit to initiate creation of the set of parallel memory transactions.

9. The device of claim 8, wherein the RAID assist unit is further configured to write a completion entry in a completion queue in the RAID assist unit upon completion of the data transfer.

10. The device of claim 6, wherein the plurality of first memory architectures is non-volatile memories (NVMs) and the second memory architecture is local memory.