Nonvolatile memory apparatus and operating method of the nonvolatile memory apparatus

• US 10,679,715 B2
• Filed: 11/08/2018
• Issued: 06/09/2020
• Est. Priority Date: 04/23/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Ko, Keun Sik
• Primary Examiner(s): King, Douglas
• Application Number:
  US16/184,817
• Publication Number:
  US 20190325976A1
• Time in Patent Office: 579 Days
• Field of Search: None
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A nonvolatile memory apparatus may include a first memory cell array, a second memory cell array, and a data sensing circuit. The first memory cell array may include a plurality of first memory cells coupled between a plurality of first word lines and a bit line. The second memory cell array may include a plurality of second memory cells coupled between a plurality of second word lines and the bit line. The data sensing circuit may define a sensing period and a latch period based on a power-up signal, may precharge a sensing node coupled to the bit line, may sense and amplify a voltage level of the sensing node, during the sensing period, and may generate an output signal by latching the sensed and amplified signal during the latch period.

Claims

1. A nonvolatile memory apparatus comprising:

a first memory cell array including a plurality of first memory cells coupled between a first of first word lines and a bit line;

a second memory cell array including a plurality of second memory cells coupled between a plurality of second word lines and the bit line; and

a data sensing circuit configured to define a sensing period and a latch period based on a power-up signal, to continuously precharge a sensing node coupled to the bit line during the sensing period, to amplify a voltage level of the sensing node during the sensing period, and to generate an output signal by latching the amplified signal during the latch period.

2. The nonvolatile memory apparatus of claim 1, wherein the latch period is within the sensing period.

3. The nonvolatile memory apparatus of claim 1, wherein the data sensing circuit comprises:

a sensing control signal generation circuit configured to generate, based on the power-up signal, a sensing enable signal for defining the sensing period and a latch enable signal for defining the latch period; and

a first sense amplifier configured to generate the output signal based on the sensing enable signal and the latch enable signal.

4. The nonvolatile memory apparatus of claim 3, wherein the sensing control signal generation circuit comprises:

a pulse generator configured to generate a control pulse signal based on the power-up signal;

a timing control signal generator configured to generate timing control signals based on the control pulse signal;

a sensing enable signal generator configured to generate the sensing enable signal based on the power-up signal and the control pulse signal; and

a latch enable signal generator configured to generate the latch enable signal based on the control pulse signal, the sensing enable signal, and the timing control signals.

5. The nonvolatile memory apparatus of claim 4, wherein the timing control signal generator comprises:

a boot-up oscillator configured to generate an oscillating signal based on the control pulse signal; and

a boot-up counter configured to generate the timing control signals by counting the oscillating signal.

6. The nonvolatile memory apparatus of claim 5,

wherein the timing control signal generator is further configured to generate a counting end signal by counting the oscillating signal, and

wherein the sensing control signal generation circuit is further configured to generate a boot-up signal based on the counting end signal.

7. The nonvolatile memory apparatus of claim 6, further comprising a second sense amplifier configured to couple to the bit line, based on the boot-up signal, and to read data stored in the plurality of second memory cells of the second memory cell array.

8. The nonvolatile memory apparatus of claim 4,

wherein the timing control signals comprise a first timing control signal and a second timing control signal, and

wherein the latch enable signal generator is further configured to enable the latch enable signal based on the first timing control signal and to disable the latch enable signal based on the second timing control signal.

9. The nonvolatile memory apparatus of claim 3, wherein the first sense amplifier comprises:

a leaker unit configured to precharge a voltage level of the sensing node based on the sensing enable signal;

an amplification unit configured to generate an amplification signal by comparing the voltage level of the sensing node with a voltage level of a reference voltage based on the sensing enable signal; and

a latch unit configured to generate the output signal by latching the amplification signal based on the latch enable signal.

10. An operating method of a nonvolatile memory apparatus comprising a first memory cell array coupled to a sensing node through a bit line, the operating method comprising:

generating a sensing enable signal based on a power-up signal;

generating an amplification signal by comparing a voltage level of the sensing node with a reference voltage based on the sensing enable signal;

precharging the sensing node together with generating the amplification signal;

generating a latch enable signal, which is enabled within an enable period of the sensing enable signal; and

generating an output signal by latching the amplification signal based on the latch enable signal.

11. The operating method of claim 10, wherein generating the latch enable signal comprises:

generating an oscillating signal based on the power-up signal and generating first and second timing control signals by counting the oscillating signal; and

enabling the latch enable signal based on the first timing control signal and disabling the latch enable signal based on the second timing control signal.

12. The operating method of claim 10,

wherein the nonvolatile memory apparatus further comprises a second memory cell array coupled to the sensing node through the bit line,

further comprising reading data stored in the second memory cell array after the generating of the output signal.