Calibration apparatus and method for sampler with adjustable high frequency gain

• US 10,679,716 B2
• Filed: 03/25/2019
• Issued: 06/09/2020
• Est. Priority Date: 04/22/2016
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin, Hormati, Ali
• Primary Examiner(s): Cox, Cassandra F
• Application Number:
  US16/363,785
• Publication Number:
  US 20190221278A1
• Time in Patent Office: 442 Days
• Field of Search: None
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H03K 2005/00013 Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
• CPC Class Codes: H03K 5/01 Shaping pulses discrimination against noise or interference H03K5/125
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling interval by enabling a current source according to a first transition of the received sampling signal, generating a differential output voltage at the pair of output nodes by discharging the pair of output nodes according to a differential input signal, the pair of output nodes discharged according to current drawn by the current source during the sampling interval, terminating the sampling interval by disabling the current source in response to a second transition of the received sampling signal, and inhibiting a recharge of the pair of output nodes for a hold time after termination of the sampling interval and prior to initiation of a subsequent sampling interval.

Claims

1. A method comprising:

initializing respective pairs of output nodes of first and second sampler stages prior to a sampling interval;

receiving a differential input voltage at an input of the first sampler stage and generating, responsive to an initiation of the sampling interval according to a clock signal, a time-varying differential voltage on the respective pair of output nodes of the first sampler stage; and

generating, responsive to the time-varying voltage on the respective pair of output nodes of the first sampler stage, a differential output voltage on the respective pair of output nodes of the second sampler stage during the sampling interval.

2. The method of claim 1, wherein the first and second sampler stages correspond to consecutive complementary stages in a cascaded integrator.

3. The method of claim 2, wherein the first and second sampler stages are made up of complementary NMOS and PMOS transistor structures.

4. The method of claim 3, wherein the first and second sampler stages receive complementary versions of the clock signal.

5. The method of claim 1, wherein initializing the respective pairs of output nodes of the first and the second sampler stages comprises pre-charging the respective pair of output nodes of the first sampler stage and pre-discharging the respective pair of output nodes of the second sampler stage.

6. The method of claim 5, wherein generating the time-varying differential voltage on the respective pair of output nodes of the first sampler stage comprises discharging the pre-charged respective pair of output nodes of the first sampler stage according to the differential input voltage;

and

generating the differential output voltage on the respective pair of output nodes of the second sampler stage comprises charging the pre-discharged respective pair of output nodes of the second sampler stage according to the time-varying differential voltage.

7. The method of claim 1, wherein initializing the respective pairs of output nodes of the first and the second sampler stages comprises pre-discharging the respective pair of output nodes of the first sampler stage and pre-charging the respective pair of output nodes of the second sampler stage.

8. The method of claim 7, wherein generating the time-varying differential voltage on the respective pair of output nodes of the first sampler stage comprises charging the pre-discharged respective pair of output nodes of the first sampler stage according to the differential input voltage;

and

generating the differential output voltage on the respective pair of output nodes of the second sampler stage comprises discharging the pre-charged respective pair of output nodes of the second sampler stage according to the time-varying differential voltage.

9. The method of claim 1, further comprising generating an output decision by slicing the differential output voltage.

10. The method of claim 1, wherein the differential output voltage is a time-varying voltage.

11. An apparatus comprising:

a reset circuit configured to initialize respective pairs of output nodes of first and second sampler stages prior to a sampling interval;

the first sampler stage configured to receive a differential input voltage at an input of the first sampler stage and to generate, responsive to an initiation of the sampling interval according to a clock signal, a time-varying differential voltage on the respective pair of output nodes of the first sampler stage; and

the second sampler stage configured to generate, responsive to the time-varying voltage on the respective pair of output nodes of the first sampler stage, a differential output voltage on the respective pair of output nodes of the second sampler stage during the sampling interval.

12. The apparatus of claim 11, wherein the first and second sampler stages correspond to consecutive complementary stages in a cascaded integrator.

13. The apparatus of claim 12, wherein the first and second sampler stages are made up of complementary NMOS and PMOS transistor structures.

14. The apparatus of claim 13, wherein the first and second sampler stages receive complementary versions of the clock signal.

15. The apparatus of claim 11, wherein the reset circuit is configured to initialize the respective pairs of output nodes of the first and the second sampler stages by pre-charging the respective pair of output nodes of the first sampler stage and pre-discharging the respective pair of output nodes of the second sampler stage.

16. The apparatus of claim 15, wherein the first sampler stage is configured to generate the time-varying differential voltage on the respective pair of output nodes of the first sampler stage by discharging the pre-charged respective pair of output nodes of the first sampler stage according to the differential input voltage;

and

the second sampler stage is configured to generate the differential output voltage on the respective pair of output nodes of the second sampler stage by charging the pre-discharged respective pair of output nodes of the second sampler stage according to the time-varying differential voltage.

17. The apparatus of claim 11, wherein the reset circuit is configured to initialize the respective pairs of output nodes of the first and the second sampler stages by pre-discharging the respective pair of output nodes of the first sampler stage and pre-charging the respective pair of output nodes of the second sampler stage.

18. The apparatus of claim 17, wherein the first sampler stage is configured to generate the time-varying differential voltage on the respective pair of output nodes of the first sampler stage by charging the pre-discharged respective pair of output nodes of the first sampler stage according to the differential input voltage;

and

the second sampler stage is configured to generate the differential output voltage on the respective pair of output nodes of the second sampler stage by discharging the pre-charged respective pair of output nodes of the second sampler stage according to the time-varying differential voltage.

19. The apparatus of claim 11, further comprising a latch configured to generate an output decision based on the differential output voltage.

20. The apparatus of claim 11, wherein the differential output voltage is a time-varying voltage.