Switching circuit

• US 10,679,823 B2
• Filed: 01/23/2019
• Issued: 06/09/2020
• Est. Priority Date: 02/18/2015
• Status: Active Grant

• Current Assignee: ASM America Incorporated (ASM International NV)
• Original Assignee: Reno Technologies Inc.
• Inventors: Mavretic, Anton, Costanzo, Ian M.
• Primary Examiner(s): Outten, Samuel S
• Application Number:
  US16/255,269
• Publication Number:
  US 20190172683A1
• Time in Patent Office: 503 Days
• CPC Class Codes: H01J 2237/334 Etching
• CPC Class Codes: H01J 37/32082 Radio frequency generated discharge H01J37/32357, H01J37/32366, H01J37/32394 and H01J37/32403 take precedence
• CPC Class Codes: H01J 37/32174 Circuits specially adapted for controlling the RF discharge
• CPC Class Codes: H01J 37/32183 Matching circuits
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/01 Resonant DC/DC converters
• CPC Class Codes: H02M 3/33569 having several active switching elements H02M3/3353 takes precedence
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H03H 7/40 Automatic matching of load impedance to source impedance
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/122 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/691 : using transformer coupling
• CPC Class Codes: H03K 17/7955 : using phototransistors
• CPC Class Codes: H03K 2017/6875 : using self-conductive, depletion FETs
• CPC Class Codes: H04B 1/0458 : Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages matching circuits in general H03H
• CPC Class Codes: H04B 1/18 : Input circuits, e.g. for coupling to an antenna or a transmission line coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H
• CPC Class Codes: H04B 1/44 : Transmit/receive switching

Abstract

In one embodiment, an impedance matching network includes at least one electronically variable capacitor (EVC), each EVC comprising discrete capacitors having corresponding switches, the switches configured to switch in and out the discrete capacitors to alter a total capacitance of the EVC. Each switch includes a first terminal operably coupled to the corresponding discrete capacitor, a second terminal, and a switching circuit coupled between the first terminal and the second terminal, the switching circuit comprising a switching transistor. A tuning inductor is coupled parallel to the switching circuit. A value for the tuning inductor enables the tuning inductor to cancel a cumulative parasitic capacitance of the switching circuit.

Claims

1. A method of matching an impedance comprising:

coupling an RF input of a matching network to an RF source;

coupling an RF output of the matching network to a plasma chamber, wherein the matching network comprises at least one electronically variable capacitor (EVC), each EVC comprising discrete capacitors having corresponding switches, the switches configured to switch in and out the discrete capacitors to alter a total capacitance of the EVC, wherein each switch comprises;

a first terminal operably coupled to the corresponding discrete capacitor;

a second terminal;

a switching circuit coupled between the first terminal and the second terminal, the switching circuit comprising;

a switching transistor;

a first switching device that, only when switched ON, passes current from the second terminal to a switching transistor second terminal;

a second switching device that, only when switched ON, passes current from the first terminal to the switching transistor second terminal;

a third switching device that, only when switched ON, passes current from a switching transistor third terminal to the first terminal; and

a fourth switching device that, only when switched ON, passes current from the switching transistor third terminal to the second terminal; and

a tuning inductor coupled parallel to the switching circuit, wherein a value for the tuning inductor enables the tuning inductor to cancel a cumulative parasitic capacitance of the switching circuit;

matching an impedance by, for at least one of the switches of the at least one EVC, turning the switching transistor ON or OFF to cause the corresponding discrete capacitor to be switched in or out.

2. The method of claim 1 wherein the parasitic capacitance comprises:

a parasitic capacitance of each of the first switching device, the second switching device, the third switching device, and the fourth switching device; and

an output capacitance of the switching transistor.

3. The method of claim 2 wherein the parasitic capacitance further comprises a packaging capacitance from a packaging of the switching transistor packaging to a ground.

4. The method of claim 1 wherein each of the first switching device, the second switching device, the third switching device, and the fourth switching device comprises a plurality of switching devices.

5. The method of claim 4 wherein the plurality of switching devices are diodes, and the switching transistor comprises a first transistor and a second transistor coupled in series.

10. The matching network of claim 1 wherein a tuning capacitor is coupled in series with the tuning inductor.

11. The matching network of claim 1 wherein the switching circuit further comprises:

a first diode whose anode is operably coupled to the second terminal and whose cathode is operably coupled to a drain of the switching transistor;

a second diode whose anode is operably coupled to the first terminal and whose cathode is operably coupled to the drain of the switching transistor and the cathode of the first diode;

a third diode whose cathode is operably coupled to the first terminal and whose anode is operably coupled to the source of the switching transistor; and

the fourth diode whose cathode is operably coupled to the second terminal and whose anode is operable coupled to the source of the switching transistor and the anode of the third diode.

12. The matching network of claim 1 wherein the switching circuit further comprises:

a first transistor having a drain coupled to the second terminal and a source coupled to a switching transistor third terminal;

a second transistor having a drain coupled to the first terminal and a source coupled to the switching transistor third terminal;

a third transistor having a source coupled to the first terminal and a drain coupled to a switching transistor second terminal; and

a fourth transistor having a source coupled to the second terminal and a drain coupled to the switching transistor second terminal.

6. An impedance matching network comprising:

a radio frequency (RF) input configured to operably couple to an RF source;

an RF output configured to operably couple to a plasma chamber; and

at least one electronically variable capacitor (EVC), each EVC comprising discrete capacitors having corresponding switches, the switches configured to switch in and out the discrete capacitors to alter a total capacitance of the EVC, wherein each switch comprises;

a first terminal operably coupled to the corresponding discrete capacitor;

a second terminal;

a switching circuit coupled between the first terminal and the second terminal, the switching circuit comprising;

a switching transistor;

a first switching device that, only when switched ON, passes current from the second terminal to a switching transistor second terminal;

a second switching device that, only when switched ON, passes current from the first terminal to the switching transistor second terminal;

a third switching device that, only when switched ON, passes current from a switching transistor third terminal to the first terminal; and

a fourth switching device that, only when switched ON, passes current from the switching transistor third terminal to the second terminal; and

a tuning inductor coupled parallel to the switching circuit, wherein a value for the tuning inductor enables the tuning inductor to cancel a cumulative parasitic capacitance of the switching circuit;

wherein for each switch, switching the switching transistor ON and OFF causes the corresponding discrete capacitor to be switched in and out.

7. The matching network of claim 6 wherein each of the first switching device, the second switching device, the third switching device, and the fourth switching device comprises a plurality of switching devices.

8. The matching network of claim 7 wherein the plurality of switching devices are diodes, and the switching transistor comprises a first transistor and a second transistor coupled in series.

9. An impedance matching network comprising:

a radio frequency (RF) input configured to operably couple to an RF source;

an RF output configured to operably couple to a plasma chamber; and

at least one electronically variable capacitor (EVC), each EVC comprising discrete capacitors having corresponding switches, the switches configured to switch in and out the discrete capacitors to alter a total capacitance of the EVC, wherein each switch comprises;

a first terminal operably coupled to the corresponding discrete capacitor;

a second terminal;

a switching circuit coupled between the first terminal and the second terminal, the switching circuit comprising a switching transistor; and

a tuning inductor coupled parallel to the switching circuit, wherein a value for the tuning inductor enables the tuning inductor to cancel a cumulative parasitic capacitance of the switching circuit;

wherein for each switch, switching the switching transistor ON and OFF causes the corresponding discrete capacitor to be switched in and out; and

wherein the switching transistor is located such that when the switching transistor is ON, current flowing between the first and second terminals flows from a switching transistor second terminal to a switching transistor third terminal both when the current is flowing in a positive direction and when the current is flowing in a negative direction.

13. A method of matching an impedance comprising:

coupling an RF input of a matching network to an RF source;

coupling an RF output of the matching network to a plasma chamber, wherein the matching network comprises at least one electronically variable capacitor (EVC), each EVC comprising discrete capacitors having corresponding switches, the switches configured to switch in and out the discrete capacitors to alter a total capacitance of the EVC, wherein each switch comprises;

a first terminal operably coupled to the corresponding discrete capacitor;

a second terminal;

a switching circuit coupled between the first terminal and the second terminal, the switching circuit comprising a switching transistor; and

a tuning inductor coupled parallel to the switching circuit, wherein a value for the tuning inductor enables the tuning inductor to cancel a cumulative parasitic capacitance of the switching circuit;

matching an impedance by, for at least one of the switches of the at least one EVC, turning the switching transistor ON or OFF to cause the corresponding discrete capacitor to be switched in or out;

wherein the switching transistor is located such that when the switching transistor is ON, current flowing between the first and second terminals flows from a switching transistor second terminal to a switching transistor third terminal both when the current is flowing in a positive direction and when the current is flowing in a negative direction.

14. The method of claim 13 wherein a tuning capacitor is coupled in series with the tuning inductor.

15. The method of claim 13 wherein the switching circuit further comprises:

a first diode whose anode is operably coupled to the second terminal and whose cathode is operably coupled to a drain of the switching transistor;

a second diode whose anode is operably coupled to the first terminal and whose cathode is operably coupled to the drain of the switching transistor and the cathode of the first diode;

a third diode whose cathode is operably coupled to the first terminal and whose anode is operably coupled to the source of the switching transistor; and

the fourth diode whose cathode is operably coupled to the second terminal and whose anode is operable coupled to the source of the switching transistor and the anode of the third diode.

16. The method of claim 13 wherein the switching circuit further comprises:

a first transistor having a drain coupled to the second terminal and a source coupled to a switching transistor third terminal;

a second transistor having a drain coupled to the first terminal and a source coupled to the switching transistor third terminal;

a third transistor having a source coupled to the first terminal and a drain coupled to a switching transistor second terminal; and

a fourth transistor having a source coupled to the second terminal and a drain coupled to the switching transistor second terminal.

17. A semiconductor processing tool comprising:

a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate; and

an impedance matching circuit operably coupled to the plasma chamber, the matching circuit comprising;

an RF input configured to operably couple to an RF source;

an RF output configured to operably couple to the plasma chamber; and

at least one electronically variable capacitor (EVC), each EVC comprising discrete capacitors having corresponding switches, the switches configured to switch in and out the discrete capacitors to alter a total capacitance of the EVC, wherein each switch comprises;

a first terminal operably coupled to the corresponding discrete capacitor;

a second terminal;

a switching circuit coupled between the first terminal and the second terminal, the switching circuit comprising a switching transistor; and

a tuning inductor coupled parallel to the switching circuit, wherein a value for the tuning inductor enables the tuning inductor to cancel a cumulative parasitic capacitance of the switching circuit;

wherein for each switch, switching the switching transistor ON and OFF causes the corresponding discrete capacitor to be switched in and out; and

wherein the switching transistor is located such that when the switching transistor is ON, current flowing between the first and second terminals flows from a switching transistor second terminal to a switching transistor third terminal both when the current is flowing in a positive direction and when the current is flowing in a negative direction.

18. A method of fabricating a semiconductor, the method comprising:

placing a substrate in a plasma chamber configured to deposit a material layer onto the substrate or etch a material layer from the substrate;

energizing plasma within the plasma chamber by coupling RF power from an RF source into the plasma chamber to perform the deposition or etching; and

while energizing the plasma, carrying out an impedance match by an impedance matching network coupled between the plasma chamber and the RF source, wherein the impedance matching network comprises;

an RF input configured to operably couple to the RF source;

an RF output configured to operably couple to the plasma chamber; and

at least one electronically variable capacitor (EVC), each EVC comprising discrete capacitors having corresponding switches, the switches configured to switch in and out the discrete capacitors to alter a total capacitance of the EVC, wherein each switch comprises;

a first terminal operably coupled to the corresponding discrete capacitor;

a second terminal;

a switching circuit coupled between the first terminal and the second terminal, the switching circuit comprising;

a first switching device that, only when switched ON, passes current from the second terminal to a switching transistor second terminal;

a second switching device that, only when switched ON, passes current from the first terminal to the switching transistor second terminal;

a third switching device that, only when switched ON, passes current from a switching transistor third terminal to the first terminal; and

a fourth switching device that, only when switched ON, passes current from the switching transistor third terminal to the second terminal; and

a tuning inductor coupled parallel to the switching circuit, wherein a value for the tuning inductor enables the tuning inductor to cancel a cumulative parasitic capacitance of the switching circuit;

wherein for each switch, switching the switching transistor ON and OFF causes the corresponding discrete capacitor to be switched in and out.