Method of forming nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness

• US 10,679,906 B2
• Filed: 07/17/2018
• Issued: 06/09/2020
• Est. Priority Date: 07/17/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Park, Chanro, Xie, Ruilong, Yamashita, Tenko
• Primary Examiner(s): Jung, Michael
• Application Number:
  US16/036,984
• Publication Number:
  US 20200027959A1
• Time in Patent Office: 693 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/4991 : comprising an air gap
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 : with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/6653 : using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 : using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78651 : Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness generally include a bilayer spacer adjacent a dummy gate disposed on a nanosheet stack. The bilayer spacer includes an inner spacer layer on sidewalls of the gate and a sacrificial layer on the inner spacer layer. The sacrificial layer can be laterally trimmed to bring the in situ doped source/drain regions closer to the channel, which improves junction sharpness. Additionally, the sacrificial spacer layer can be later removed during the process for forming the transistor so as to form an airgap spacer adjacent the gate, which minimizes parasitic capacitance.

Claims

1. A method for forming a nanosheet transistor with reduced parasitic capacitance and improved junction sharpness, the method comprising:

depositing a bilayer comprising an inner spacer layer and a sacrificial layer on a dummy gate, wherein the dummy gate is formed on a nanosheet stack comprising Si layers and SiGe layers;

laterally etching the SiGe layers relative to the Si layers such that W is greater than t, wherein W is a lateral etch width and t is a gap distance between Si layers;

forming an inner spacer adjacent the SiGe layers having a width such that the Si layers have exposed end portions;

epitaxially growing source/drain regions from the exposed end portions of the Si layers;

depositing an interlevel dielectric layer;

selectively removing the dummy gate and remaining portions of the SiGe layers and depositing a high-k dielectric-metal gate structure therein;

forming contacts in the interlevel dielectric layer to the source/drain regions;

selectively removing the sacrificial layer to form a gap between the inner spacer layers adjacent the high-k dielectric-metal gate structure and the contacts; and

non-conformally depositing a dielectric into the gap to form an airgap spacer therein.

2. The method of claim 1, wherein the inner spacer of the bilayer comprises SiBCN and the sacrificial layer comprises SiCO.

3. The method of claim 1, wherein laterally etching the SiGe layers from the nanosheet stacks comprises exposing the SiGe layers to HCl vapor.

4. The method of claim 1, wherein forming the inner spacer adjacent the SiGe layers comprises conformally depositing a dielectric layer at a thickness effective to pinch off between the Si layers followed by etch back with an overetch to provide the exposed end portions of the Si layers.

5. The method of claim 4, wherein the dielectric layer comprises silicon nitride.

6. The method of claim 1 further comprising laterally trimming the sacrificial layer prior to depositing the interlevel dielectric layer to provide a recess between the inner spacer layer about the high-k dielectric-metal gate structure and an inner sidewall of the source/drain region.

7. The method of claim 6, wherein forming the contacts in the interlevel dielectric layer to the source/drain regions fills the recess.

8. The method of claim 6, wherein the SiGe has a germanium content from about 5 atomic percent to about 70 atomic percent.

9. A method for forming a nanosheet transistor with reduced parasitic capacitance and improved junction sharpness, the method comprising:

depositing a dummy gate onto the nanosheet stack and sidewalls thereof, the nanosheet stack comprising epitaxially deposited silicon layers sandwiched between SiGe layers;

depositing a bilayer spacer onto sidewalls of the dummy gate comprising a SiBCN layer in direct contact with the sidewalls and a SiCO sacrificial layer on the SiBCN layer;

recessing the nanosheet stack to form openings for source or drain regions, wherein the openings are self-aligned to the SiCO sacrificial layer;

laterally etching the SiGe layers to create a gap between Si layers, wherein W>

t, wherein W is a lateral etch width of the SiGe removed and t is a vertical distance between Si layers;

conformally depositing a first dielectric layer in an amount effective to fill the gap between the Si layers;

etching back the first dielectric layer to form an inner spacer layer of the first dielectric on sidewalls of the SiGe layers and expose end portions of the Si layers;

epitaxially growing the source/drain regions from the exposed end portions of the Si layers to the substrate;

removing the dummy gate and the SiGe layer between the Si layers to form openings therein;

forming a high-k dielectric-metal gate structure in the openings;

recessing a top portion of the high-k dielectric-metal gate structure and depositing a dielectric gate cap therein;

forming contacts to the source or drain regions;

selectively removing the SiCO sacrificial spacer layer to form a gap between the high-k dielectric-metal gate structure and the contacts; and

non-conformally depositing a second dielectric in the gap for form an airgap spacer.

10. The method of claim 9 further comprising planarizing the structure to the gate cap.

11. The method of claim 9, wherein the dielectric layer comprises silicon nitride.

12. The method of claim 9, wherein the substrate includes a buried oxide layer.

13. The method of claim 9, wherein selectively removing the SiGe layers from the nanosheet stacks comprises exposing the SiGe layers to HCl vapor.

14. The method of claim 9 further comprising laterally trimming the SiCO sacrificial layer subsequent to epitaxially growing the source/drain regions to form a recess between the inner SiBCN spacer and an inner sidewall of the source/drain regions.

15. The method of claim 14, wherein forming contacts to the source or drain regions fills the recess.