Wafer scale testing and initialization of small die chips

• US 10,679,912 B2
• Filed: 10/02/2017
• Issued: 06/09/2020
• Est. Priority Date: 10/02/2017
• Status: Active Grant

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Horibe, Akihiro, Kohda, Yasuteru, Munetoh, Seiji, Subramanian, Chitra, Sueoka, Kuniaki
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US15/722,409
• Publication Number:
  US 20190103327A1
• Time in Patent Office: 981 Days
• Field of Search: 257 48, 257620
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/30 Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1434 Memory

Abstract

A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.

Claims

1. A chip intermediate body, comprising:

a semiconductor region cut from a wafer, with the semiconductor region including a plurality of chip areas, the chip areas respectively being cut out as semiconductor chips;

a cut region provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips;

a test region provided opposite to the chip areas across the cut region in parallel with a side of the cut region, the test region including a plurality of test circuits, with each of the plurality, of test circuits corresponding to a group of the chip areas;

a contact region provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas; and

an insulating layer with embedded electric wiring provided continuously with the cut region to connect the chip areas, the test region, and the contact region.

2. The chip intermediate body of claim 1, wherein each of the chip areas includes bumps on a surface of the chip area.

3. The chip intermediate body of claim 2, wherein

the contact region includes a plurality of test pads,

the test pads are configured to be contacted by respective contact points of the probe of the test unit, and

each of the test pads has a larger area than each of the bumps.

4. The chip intermediate body of claim 1, wherein the cut region includes other electric wiring that at least interconnects the chip areas and connects the chip areas and the contact region.

5. The chip intermediate body of claim 4, wherein the other electric wiring is electrically connected with the electric wiring.

6. The chip intermediate body of claim 4, wherein each of the chip areas includes circuit wiring, and

the other electric wiring and the circuit wiring are present in the same layer of the chip intermediate body.

7. The chip intermediate body of claim 6, wherein the circuit wiring is set apart from a boundary between the chip areas and the cut region.

8. The chip intermediate body of claim 1, wherein the chip intermediate body is a plate member and has a generally square shape in a plane view.

9. The chip intermediate body of claim 8, wherein the contact region is provided along edges of the chip intermediate body.

10. A chip intermediate body manufacturing system for manufacturing a chip intermediate body, the chip intermediate body comprising:

a semiconductor region cut from a wafer, with the semiconductor region including a plurality of chip areas, the chip areas respectively being cut out as semiconductor chips;

a cut region provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips;

a test region provided opposite to the chip areas across the cut region in parallel with a side of the cut region, the test region including a plurality of test circuits, with each of the plurality of test circuits corresponding to a group of the chip areas;

a contact region provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas; and

an insulating layer with embedded electric wiring provided continuously with the cut region to connect the chip areas, the test region, and the contact region.

11. A semiconductor chip manufacturing system, comprising;

a fabrication unit for fabricating a chip intermediate body including a semiconductor region cut from a wafer, a cut region, a test region, a contact region, and electric wiring, the semiconductor region including a plurality of chip areas respectively cut out as semiconductor chips, the cut region being provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips, the test region provided opposite to the chip areas across the cut region, the test region including a plurality of test circuits, with each of the plurality of test circuits corresponding to a group of the chip areas, the contact region being provided opposite to the chip areas across the cut region, the electric wiring being embedded in an insulating layer and provided continuously with the cut region to connect the chip areas, the test region, and the contact region;

a test unit for testing the chip areas, the test unit provided in parallel with a side of the cut region including a probe to contact the contact region to test the chip areas; and

a separation unit for cutting the cut region to cut out the semiconductor chips.