Devices and methods of forming low resistivity noble metal interconnect

• US 10,679,937 B2
• Filed: 10/17/2017
• Issued: 06/09/2020
• Est. Priority Date: 05/31/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Zhang, Xunyuan, Mont, Frank W., Ryan, Errol Todd
• Primary Examiner(s): Pizarro, Marcos D.
• Assistant Examiner(s): Crite, Antonio B
• Application Number:
  US15/785,665
• Publication Number:
  US 20180040555A1
• Time in Patent Office: 966 Days
• CPC Class Codes: H01L 21/02244 of a metallic layer
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers

Abstract

Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

Claims

1. A structure comprising:

a dielectric matrix;

a first via extending completely through the dielectric matrix;

a second via extending completely through the dielectric matrix;

a trench extending partially through the dielectric matrix, the trench arranged laterally between the first via and the second via;

a first interconnect in the first via;

a second interconnect in the second via;

a third interconnect in the trench;

a barrier layer including a first portion and a second portion lining each of the first via, the second via, and the trench,

a first air-gap arranged laterally between the trench and the first via; and

a second air-gap arranged laterally between the trench and the second via,

wherein the first portion of the barrier layer is an oxide, the second portion of the barrier layer is a metal, the first air-gap and the second air-gap are fully surrounded by respective portions of dielectric material, and the first interconnect, the second interconnect, and the third interconnect each comprise a noble metal.

2. The structure of claim 1, wherein the oxide is tantalum oxide or titanium oxide.

3. The structure of claim 1, wherein the first air-gap and the second air-gap are fully located at a depth above a depth of the trench.

4. The structure of claim 1, wherein the second portion of the barrier layer is positioned below the first portion of the barrier layer in the first via, in the second via, and in the trench.

5. The structure of claim 1, wherein the noble metal is ruthenium, niobium, rhodium, iridium, or platinum.

6. The structure of claim 1, wherein the first interconnect, the second interconnect, and the third interconnect have a line width in a range of 6 nm to 20 nm.

7. The structure of claim 6, wherein the noble metal is ruthenium.

8. A structure comprising:

a dielectric matrix;

a first via extending completely through the dielectric matrix;

a second via extending completely through the dielectric matrix;

a trench extending partially through the dielectric matrix, the trench arranged laterally between the first via and the second via;

a first interconnect in the first via;

a second interconnect in the second via;

a third interconnect in the trench;

a first air-gap arranged laterally between the trench and the first via;

a second air-gap arranged laterally between the trench and the second via; and

a barrier layer having respective portions lining the first via, the second via, and the trench, the respective portions of the barrier layer located in the first via, in the second via, and in the trench below respective portions of dielectric material

wherein the respective portions of dielectric material directly contact the first interconnect, the second interconnect, and the third interconnect, the first air-gap and the second air-gap are fully surrounded by therespective portions of dielectric material, and the first interconnect, the second interconnect, and the third interconnect each comprise a noble metal.

9. The structure of claim 8, wherein the noble metal is ruthenium, niobium, rhodium, iridium, or platinum.

10. The structure of claim 8, wherein the first air-gap and the second air-gap are fully located at a depth above a depth of the trench.

11. The structure of claim 8, wherein the first interconnect, the second interconnect, and the third interconnect have a line width in a range of 6 nm to 20 nm.

12. The structure of claim 11, wherein the noble metal is ruthenium.