III-V semiconductor layers, III-V semiconductor device and methods of manufacturing thereof

• US 10,680,062 B2
• Filed: 04/12/2019
• Issued: 06/09/2020
• Est. Priority Date: 11/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Van Dal, Mark, Doornbos, Gerben, Passlack, Matthias, Holland, Martin Christopher
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US16/383,528
• Publication Number:
  US 20190245037A1
• Time in Patent Office: 424 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A gate-all-around field effect transistor (GAA FET) includes an InAs nano-wire as a channel layer, a gate dielectric layer wrapping the InAs nano-wire, and a gate electrode metal layer formed on the gate dielectric layer. The InAs nano-wire has first to fourth major surfaces three convex-rounded corner surfaces and one concave-rounded corner surface.

Claims

1. A gate-all-around field effect transistor (GAA FET), comprising:

a nano-wire made of a Group III-V semiconductor as a channel layer;

a gate dielectric layer wrapping the nano-wire; and

a gate electrode metal layer formed on the gate dielectric layer, wherein;

the nano-wire has first, second, third and fourth major faces, first, second and third convex-rounded corner faces and one concave-rounded corner face.

2. The GAA FET of claim 1, wherein the Group III-V semiconductor is InAs.

3. The GAA FET of claim 1, further comprising:

a bottom fin structure, over which the nano-wire is disposed and which extends along a first direction,

wherein the gate electrode metal layer extends along a second direction crossing the first direction.

4. The GAA FET of claim 3, wherein in the second direction, a width of the nano-wire covered by the gate electrode metal layer is greater than a width of the bottom fin structure.

5. The GAA FET of claim 4, wherein an upper surface of the bottom fin structure has a V-shaped concave shape.

6. The GAA FET of claim 5, wherein the width of the bottom fin structure is measured at a bottom of the V-shaped concave shape.

7. The GAA FET of claim 4, wherein the gate dielectric layer is also formed on an upper surface of the bottom fin structure.

8. The GAA FET of claim 4, further comprising a void disposed in the gate electrode metal layer between the nano-wire and the bottom fin structure.

9. The GAA FET of claim 8, further comprising a source and a drain,

wherein the void extends below the source and the drain.

10. The GAA FET of claim 4, wherein no void is disposed in the gate electrode metal layer between the nano-wire and the bottom fin structure.

11. The GAA FET of claim 1, wherein:

the first convex-rounded corner face connects the first major face and the second major face,

the concave-rounded corner face connects the second major face and the third major face,

the second convex-rounded corner face connects the third major face and the fourth major face, and

the third convex-rounded corner face connects the fourth major face and the first major face.

12. The GAA FET of claim 1, wherein:

extended planes of the first major face and the second major face make an acute angle,

extended planes of the second major face and the third major face make an angle of 60°

to 150°

,

extended planes of the third major face and the fourth major face make an acute angle, and

extended planes of the fourth major face and the first major face make an acute angle.

13. The GAA FET of claim 12, wherein the extended planes of the second major face and the third major face make an angle of 90°

to 150°

.

14. A gate-all-around field effect transistor (GAA FET), comprising:

a bottom fin structure extending in a first direction;

an InAs nano-wire as a channel layer; and

a gate electrode extending in a second direction crossing the first direction, and including a gate dielectric layer wrapping the InAs nano-wire and a gate electrode metal layer formed on the gate dielectric layer, wherein;

the InAs nano-wire has a triangular cross section with rounded corners, and

in the second direction, a width of the InAs nano-wire under the gate electrode is greater than a width of the bottom fin structure.

15. The GAA FET of claim 14, wherein an upper surface of the bottom fin structure has a V-shaped concave shape.

16. The GAA FET of claim 15, wherein the width of the bottom fin structure is measured at a bottom of the V-shaped concave shape.

17. The GAA FET of claim 14, wherein the gate dielectric layer is also formed on an upper surface of the bottom fin structure.

18. The GAA FET of claim 14, further comprising a void disposed in the gate electrode metal layer between the nano-wire and the bottom fin structure.

19. The GAA FET of claim 18, further comprising a source region and a drain,

wherein the void extends below the source and the drain.

20. A gate-all-around field effect transistor (GAA FET), comprising:

a bottom fin structure extending in a first direction;

an InAs nano-wire as a channel layer; and

a gate electrode extending in a second direction crossing the first direction, and including a gate dielectric layer wrapping the InAs nano-wire and a gate electrode metal layer formed on the gate dielectric layer, wherein;

the InAs nano-wire has a boomerang shape cross section, and

in the second direction, a width of the InAs nano-wire under the gate electrode is greater than a width of the bottom fin structure.