Enclosed gate runner for eliminating miller turn-on

• US 10,680,090 B2
• Filed: 07/20/2017
• Issued: 06/09/2020
• Est. Priority Date: 07/20/2017
• Status: Active Grant

• Current Assignee: Ancora Semiconductors Incorporated
• Original Assignee: Delta Electronics Incorporated
• Inventors: Liao, Wen-Chia, Liu, Ying-Chen, Chiang, Chen-Ting
• Primary Examiner(s): Campbell, Shaun M
• Assistant Examiner(s): Chi, Suberr L
• Application Number:
  US15/655,241
• Publication Number:
  US 20190027593A1
• Time in Patent Office: 1,055 Days
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence

Abstract

A semiconductor structure is provided, which includes a semiconductor device, a first conductive layer, and a gate runner. The semiconductor device includes an upper surface, a gate terminal, a source terminal, and a drain terminal. The first conductive layer is deposited on the upper surface and coupled to the source terminal. The gate runner is overlapped with the first conductive layer and coupled to the gate terminal. The gate runner and the first conductive layer are configured to contribute a parasitic capacitance between the gate terminal and the source terminal.

Claims

1. A semiconductor structure, comprising:

a semiconductor device, comprising an upper surface, a gate terminal, a source terminal, and a drain terminal;

a first conductive layer, deposited above the upper surface and coupled to the source terminal, wherein the first conductive layer is a field plate;

a gate runner, overlapped with the first conductive layer and coupled to the gate terminal, wherein the gate runner and the first conductive layer are configured to contribute to a first portion of a parasitic capacitance between the gate terminal and the source terminal, wherein the gate runner is deposited above the first conductive layer;

a second conductive layer, deposited above the gate runner and the first conductive layer and coupled to the source terminal, wherein the second conductive layer and the gate runner are configured to contribute to a second portion of the parasitic capacitance between the gate terminal and the source terminal;

a first insulating layer, deposited between the gate runner and the second conductive layer;

a metal layer, deposited above the second conductive layer and coupled to the gate terminal, wherein the second conductive layer and the metal layer contribute to a third portion of the parasitic capacitance between the gate terminal and the source terminal; and

a second insulating layer, deposited between the metal layer and the second conductive layer.

2. The semiconductor structure of claim 1, further comprising:

a third insulating layer, deposited between the first conductive layer and the upper surface; and

a fourth insulating layer, deposited between the first conductive layer and the gate runner.

3. The semiconductor structure of claim 1, wherein the first conductive layer is divided into a first part and a second part, wherein the gate runner is overlapped with the first part and the second part.

4. The semiconductor structure of claim 1, wherein the first conductive layer is staggered with the gate runner.

5. The semiconductor structure of claim 1, wherein the second conductive layer is a field plate.

6. The semiconductor structure of claim 1, wherein the second conductive layer has an opening, wherein the gate runner is electrically coupled to the metal layer through the opening.

7. The semiconductor structure of claim 1, wherein the gate runner is deposited between the first conductive layer and the upper surface.

8. A semiconductor structure, comprising:

a III-V device, comprising an upper surface, a gate terminal, a source terminal, and a drain terminal;

a first conductive layer, deposited above the upper surface and coupled to the source terminal, wherein the first conductive layer is a field plate;

a gate runner, overlapped with the first conductive layer and coupled to the gate terminal, wherein the gate runner and the first conductive layer contribute to a first portion of a parasitic capacitance between the gate terminal and the source terminal, wherein the gate runner is deposited above the first conductive layer;

a second conductive layer, deposited above the gate runner and the first conductive layer and coupled to the source terminal, wherein the second conductive layer and the gate runner contribute to a second portion of the parasitic capacitance between the gate terminal and the source terminal;

a first insulating layer, deposited between the gate runner and the second conductive layer;

a metal layer, deposited above the second conductive layer and coupled to the gate terminal, wherein the second conductive layer and the metal layer are configured to contribute to a third portion of the parasitic capacitance between the gate terminal and the source terminal; and

a second insulating layer, deposited between the metal layer and the second conductive layer.

9. The semiconductor structure of claim 8, further comprising:

a third insulating layer, deposited between the first conductive layer and the upper surface; and

a fourth insulating layer, deposited between the first conductive layer and the gate runner.

10. The semiconductor structure of claim 8, wherein the first conductive layer is staggered with the gate runner.

11. The semiconductor structure of claim 8, wherein the second conductive layer is a field plate.

12. The semiconductor structure of claim 8, wherein the second conductive layer has an opening, wherein the gate runner is electrically coupled to the metal layer through the opening.

13. The semiconductor structure of claim 8, wherein the gate runner is deposited between the first conductive layer and the upper surface.

14. The semiconductor structure of claim 8, wherein the III-V device is a GaN HEMT.

15. The semiconductor structure of claim 8, wherein the III-V device is an enhancement mode HEMT.