Oxide semiconductor device

• US 10,680,111 B2
• Filed: 09/05/2018
• Issued: 06/09/2020
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Hosoba, Miyuki, Sakata, Junichiro, Kuwabara, Hideaki
• Primary Examiner(s): Yushin, Nikolay K
• Application Number:
  US16/121,708
• Publication Number:
  US 20190019895A1
• Time in Patent Office: 643 Days
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/167 by electrophoresis
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/344 based on particles moving in a fluid or in a gas, e.g. electrophoretic devices electrophoretic devices per se G02F1/167
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 29/45 : Ohmic electrodes
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 : of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/786 : Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78606 : with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs

Abstract

An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

Claims

1. A semiconductor device comprising:

a gate electrode over a substrate;

a silicon nitride layer over the gate electrode;

a first silicon oxide layer over and in contact with the silicon nitride layer;

an oxide semiconductor layer over and in contact with the first silicon oxide layer;

a second silicon oxide layer comprising a region in contact with a channel formation region of the oxide semiconductor layer, and a region covering a periphery portion of the oxide semiconductor layer;

a first conductive layer and a second conductive layer over and in contact with the second silicon oxide layer;

a third silicon oxide layer comprising a region in contact with the first conductive layer, and a region in contact with the second conductive layer; and

a planarizing insulating layer over the third silicon oxide layer, the planarizing insulating layer comprising an organic material,

wherein each of the first conductive layer and the second conductive layer comprises a region in contact with the oxide semiconductor layer through a first opening provided in the second silicon oxide layer, and

wherein the first opening overlaps with the gate electrode.

2. The semiconductor device according to claim 1, wherein each of the first conductive layer and the second conductive layer comprises a layer comprising Ti and a layer comprising Cu.

3. The semiconductor device according to claim 1, further comprising an inorganic insulating layer between the third silicon oxide layer and the planarizing insulating layer.

4. A semiconductor device comprising:

a gate electrode over a substrate;

a silicon nitride layer over the gate electrode;

a first silicon oxide layer over and in contact with the silicon nitride layer;

an oxide semiconductor layer over and in contact with the first silicon oxide layer;

a second silicon oxide layer comprising a region in contact with a channel formation region of the oxide semiconductor layer, and a region covering a periphery portion of the oxide semiconductor layer;

a first conductive layer and a second conductive layer over and in contact with the second silicon oxide layer;

a third silicon oxide layer comprising a region in contact with the first conductive layer, and a region in contact with the second conductive layer;

a third conductive layer comprising a region overlapping with the oxide semiconductor layer with the second silicon oxide layer and the third silicon oxide layer therebetween; and

a planarizing insulating layer over the third silicon oxide layer, the planarizing insulating layer comprising an organic material,

wherein an entirety of the oxide semiconductor layer overlaps with the gate electrode,

wherein each of the first conductive layer and the second conductive layer comprises a region in contact with the oxide semiconductor layer through a first opening provided in the second silicon oxide layer, and

wherein the first opening overlaps with the gate electrode.

5. The semiconductor device according to claim 4, wherein the third conductive layer is positioned over the planarizing insulating layer.

6. The semiconductor device according to claim 4, wherein the third conductive layer is electrically connected to the gate electrode.

7. The semiconductor device according to claim 4, wherein each of the first conductive layer and the second conductive layer comprises a layer comprising Ti and a layer comprising Cu.

8. The semiconductor device according to claim 4, further comprising an inorganic insulating layer between the third silicon oxide layer and the planarizing insulating layer.

9. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating film over the gate electrode;

an oxide semiconductor layer over the gate insulating film;

a first silicon oxide layer comprising a region in contact with a channel formation region of the oxide semiconductor layer, and a region covering a periphery portion of the oxide semiconductor layer;

a first conductive layer over and in contact with the first silicon oxide layer;

a second conductive layer over and in contact with the first silicon oxide layer;

a second silicon oxide layer comprising a region in contact with the first silicon oxide layer, a region in contact with the first conductive layer, and a region in contact with the second conductive layer; and

a planarizing insulating layer over the second silicon oxide layer, the planarizing insulating layer comprising an organic material,

wherein the first conductive layer comprises a region in contact with the oxide semiconductor layer through a first opening provided in the first silicon oxide layer,

wherein the second conductive layer comprises a region in contact with the oxide semiconductor layer through a second opening provided in the first silicon oxide layer,

wherein each of the first conductive layer and the second conductive layer comprises a stack of two or more layers,

wherein the stack comprises a layer comprising Cu or a layer comprising Ti,

wherein the first conductive layer comprises a region overlapping with the gate electrode with the gate insulating film, the oxide semiconductor layer, and the first silicon oxide layer therebetween in a channel length direction of the oxide semiconductor layer, and

wherein the second conductive layer comprises a region overlapping with the gate electrode with the gate insulating film, the oxide semiconductor layer, and the first silicon oxide layer therebetween in the channel length direction of the oxide semiconductor layer.

10. A semiconductor device comprising:

a gate electrode over a substrate;

a silicon nitride layer over the gate electrode;

a first silicon oxide layer over and in contact with the silicon nitride layer;

an oxide semiconductor layer over and in contact with the first silicon oxide layer;

a second silicon oxide layer comprising a region in contact with a channel formation region of the oxide semiconductor layer, and a region covering a periphery portion of the oxide semiconductor layer;

a first conductive layer over and in contact with the second silicon oxide layer;

a second conductive layer over and in contact with the second silicon oxide layer;

a third silicon oxide layer comprising a region in contact with the second silicon oxide layer, a region in contact with the first conductive layer, and a region in contact with the second conductive layer; and

a planarizing insulating layer over the second silicon oxide layer, the planarizing insulating layer comprising an organic material,

wherein the first conductive layer comprises a region in contact with the oxide semiconductor layer through a first opening provided in the first silicon oxide layer,

wherein the second conductive layer comprises a region in contact with the oxide semiconductor layer through a second opening provided in the first silicon oxide layer,

wherein each of the first conductive layer and the second conductive layer comprises a stack of two or more layers,

wherein the stack comprises a layer comprising Cu or a layer comprising Ti,

wherein the first conductive layer comprises a region overlapping with the gate electrode with the silicon nitride layer, the first silicon oxide layer, the oxide semiconductor layer, and the second silicon oxide layer therebetween in a channel length direction of the oxide semiconductor layer, and

wherein the second conductive layer comprises a region overlapping with the gate electrode with the silicon nitride layer, the first silicon oxide layer, the oxide semiconductor layer, and the second silicon oxide layer therebetween in the channel length direction of the oxide semiconductor layer.

11. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating film over the gate electrode;

an oxide semiconductor layer over the gate insulating film;

a first silicon oxide layer comprising a region in contact with a channel formation region of the oxide semiconductor layer, and a region covering a periphery portion of the oxide semiconductor layer;

a first conductive layer over and in contact with the first silicon oxide layer;

a second conductive layer over and in contact with the first silicon oxide layer;

a second silicon oxide layer comprising a region in contact with the first silicon oxide layer, a region in contact with the first conductive layer, and a region in contact with the second conductive layer; and

a planarizing insulating layer over the second silicon oxide layer, the planarizing insulating layer comprising an organic material,

wherein the oxide semiconductor layer comprises In, Ga, and Zn,

wherein the first conductive layer comprises a region in contact with the oxide semiconductor layer through a first opening provided in the first silicon oxide layer,

wherein the second conductive layer comprises a region in contact with the oxide semiconductor layer through a second opening provided in the first silicon oxide layer,

wherein each of the first conductive layer and the second conductive layer comprises a stack of two or more layers,

wherein the stack comprises a layer comprising Cu or a layer comprising Ti,

wherein the first conductive layer comprises a region overlapping with the gate electrode with the gate insulating film, the oxide semiconductor layer, and the first silicon oxide layer therebetween in a channel length direction of the oxide semiconductor layer, and

wherein the second conductive layer comprises a region overlapping with the gate electrode with the gate insulating film, the oxide semiconductor layer, and the first silicon oxide layer therebetween in the channel length direction of the oxide semiconductor layer.

12. A semiconductor device comprising:

a gate electrode over a substrate;

a silicon nitride layer over the gate electrode;

a first silicon oxide layer over and in contact with the silicon nitride layer;

an oxide semiconductor layer over and in contact with the first silicon oxide layer;

a second silicon oxide layer comprising a region in contact with a channel formation region of the oxide semiconductor layer, and a region covering a periphery portion of the oxide semiconductor layer;

a first conductive layer over and in contact with the second silicon oxide layer;

a second conductive layer over and in contact with the second silicon oxide layer;

a third silicon oxide layer comprising a region in contact with the second silicon oxide layer, a region in contact with the first conductive layer, and a region in contact with the second conductive layer; and

a planarizing insulating layer over the second silicon oxide layer, the planarizing insulating layer comprising an organic material,

wherein the oxide semiconductor layer comprises In, Ga, and Zn,

wherein the first conductive layer comprises a region in contact with the oxide semiconductor layer through a first opening provided in the first silicon oxide layer,

wherein the second conductive layer comprises a region in contact with the oxide semiconductor layer through a second opening provided in the first silicon oxide layer,

wherein each of the first conductive layer and the second conductive layer comprises a stack of two or more layers,

wherein the stack comprises a layer comprising Cu or a layer comprising Ti,

wherein the first conductive layer comprises a region overlapping with the gate electrode with the silicon nitride layer, the first silicon oxide layer, the oxide semiconductor layer, and the second silicon oxide layer therebetween in a channel length direction of the oxide semiconductor layer, and

wherein the second conductive layer comprises a region overlapping with the gate electrode with the silicon nitride layer, the first silicon oxide layer, the oxide semiconductor layer, and the second silicon oxide layer therebetween in the channel length direction of the oxide semiconductor layer.

13. A semiconductor device comprising:

a gate electrode over and in direct contact with a substrate;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising a region overlapping with the gate electrode;

a first oxide insulating layer over the oxide semiconductor layer, the first oxide insulating layer being a single layer;

a source electrode over the first oxide insulating layer;

a drain electrode over the first oxide insulating layer;

a second oxide insulating layer over the first oxide insulating layer, the source electrode, and the drain electrode,

a planarizing insulating layer over the second oxide insulating layer; and

a pixel electrode over the planarizing insulating layer, the pixel electrode electrically connected to the source electrode or the drain electrode,

wherein the source electrode is electrically connected to the oxide semiconductor layer through a first opening provided in the first oxide insulating layer,

wherein the drain electrode is electrically connected to the oxide semiconductor layer through a second opening provided in the first oxide insulating layer,

wherein each of the source electrode and the drain electrode comprises a first conductive layer comprising a region in direct contact with the oxide semiconductor layer and the first oxide insulating layer, and a second conductive layer over the first conductive layer,

wherein the first conductive layer comprises Ti,

wherein the second conductive layer comprises Cu,

wherein the first oxide insulating layer comprises a region in direct contact with a channel formation region of the oxide semiconductor layer, and a region covering a periphery portion of the oxide semiconductor layer,

wherein the second oxide insulating layer comprises a first region in direct contact with the first oxide insulating layer and a second region in direct contact with the oxide semiconductor layer, and

wherein the oxide semiconductor layer comprises at least In, Ga, and Zn.

14. A semiconductor device comprising:

a gate electrode over and in direct contact with a substrate;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising a region overlapping with the gate electrode;

a first oxide insulating layer over the oxide semiconductor layer, the first oxide insulating layer being a single layer;

a source electrode over the first oxide insulating layer;

a drain electrode over the first oxide insulating layer;

a second oxide insulating layer over the first oxide insulating layer, the source electrode, and the drain electrode,

a planarizing insulating layer over the second oxide insulating layer; and

a pixel electrode over the planarizing insulating layer, the pixel electrode electrically connected to the source electrode or the drain electrode,

wherein the source electrode is electrically connected to the oxide semiconductor layer through a first opening provided in the first oxide insulating layer,

wherein the drain electrode is electrically connected to the oxide semiconductor layer through a second opening provided in the first oxide insulating layer,

wherein the first oxide insulating layer comprises a region in direct contact with a channel formation region of the oxide semiconductor layer, and a region covering a periphery portion of the oxide semiconductor layer,

wherein the second oxide insulating layer comprises a first region in direct contact with the first oxide insulating layer and a second region in direct contact with the oxide semiconductor layer, and

wherein the oxide semiconductor layer comprises a region comprising a crystal.

15. A semiconductor device comprising:

a gate electrode over and in direct contact with a substrate;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising a region overlapping with the gate electrode;

a first oxide insulating layer over the oxide semiconductor layer, the first oxide insulating layer being a single layer;

a source electrode over the first oxide insulating layer;

a drain electrode over the first oxide insulating layer;

a second oxide insulating layer over the first oxide insulating layer, the source electrode, and the drain electrode,

a layer comprising a resin, over the second oxide insulating layer; and

a pixel electrode over the layer comprising the resin, the pixel electrode electrically connected to the source electrode or the drain electrode,

wherein the source electrode is electrically connected to the oxide semiconductor layer through a first opening provided in the first oxide insulating layer,

wherein the drain electrode is electrically connected to the oxide semiconductor layer through a second opening provided in the first oxide insulating layer,

wherein each of the source electrode and the drain electrode comprises a first conductive layer comprising a region in direct contact with the oxide semiconductor layer and the first oxide insulating layer, and a second conductive layer over the first conductive layer,

wherein the first conductive layer comprises Ti,

wherein the second conductive layer comprises Cu,

wherein the first oxide insulating layer comprises a region in direct contact with a channel formation region of the oxide semiconductor layer, and a region covering a periphery portion of the oxide semiconductor layer,

wherein the second oxide insulating layer comprises a first region in direct contact with the first oxide insulating layer and a second region in direct contact with the oxide semiconductor layer, and

wherein the oxide semiconductor layer comprises at least In, Ga, and Zn.

16. A semiconductor device comprising:

a gate electrode over and in direct contact with a substrate;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising a region overlapping with the gate electrode;

a first oxide insulating layer over the oxide semiconductor layer, the first oxide insulating layer being a single layer;

a source electrode over the first oxide insulating layer;

a drain electrode over the first oxide insulating layer;

a second oxide insulating layer over the first oxide insulating layer, the source electrode, and the drain electrode,

a layer comprising a resin, over the second oxide insulating layer; and

a pixel electrode over the layer comprising the resin, the pixel electrode electrically connected to the source electrode or the drain electrode,

wherein the source electrode is electrically connected to the oxide semiconductor layer through a first opening provided in the first oxide insulating layer,

wherein the drain electrode is electrically connected to the oxide semiconductor layer through a second opening provided in the first oxide insulating layer,

wherein the first oxide insulating layer comprises a region in direct contact with a channel formation region of the oxide semiconductor layer, and a region covering a periphery portion of the oxide semiconductor layer,

wherein the second oxide insulating layer comprises a first region in direct contact with the first oxide insulating layer and a second region in direct contact with the oxide semiconductor layer, and

wherein the oxide semiconductor layer comprises a region comprising a crystal.

17. A semiconductor device comprising:

a first wiring over and in direct contact with a substrate;

a gate insulating layer over the first wiring;

a first oxide semiconductor layer over the gate insulating layer, the first oxide semiconductor layer comprising a region overlapping with the first wiring;

a first oxide insulating layer over the first oxide semiconductor layer, the first oxide insulating layer being a single layer;

a second wiring over the first oxide insulating layer;

a first electrode over the first oxide insulating layer;

a second oxide insulating layer over the first oxide insulating layer, the second wiring, and the first electrode; and

a first protection circuit electrically connected to the first wiring or the second wiring,

wherein the first wiring comprises a region capable of functioning as a gate electrode,

wherein the second wiring comprises a region capable of functioning as a source electrode or a drain electrode,

wherein the second wiring is electrically connected to the first oxide semiconductor layer through a first opening provided in the first oxide insulating layer,

wherein the first electrode is electrically connected to the first oxide semiconductor layer through a second opening provided in the first oxide insulating layer,

wherein the first oxide insulating layer comprises a region in direct contact with a channel formation region of the first oxide semiconductor layer, and a region covering a periphery portion of the first oxide semiconductor layer,

wherein the second oxide insulating layer comprises a first region in direct contact with the first oxide insulating layer and a second region in direct contact with the first oxide semiconductor layer,

wherein the first protection circuit comprises a non-linear element comprising a second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises at least In, Ga, and Zn, and

wherein the second oxide semiconductor layer comprises at least In, Ga, and Zn.

18. A semiconductor device comprising:

a gate electrode layer;

a first insulating layer over the gate electrode layer;

an oxide semiconductor film overlapping the gate electrode layer with the first insulating layer therebetween;

an oxide insulating layer over the oxide semiconductor film;

an electrode layer in contact with a first region of the oxide semiconductor film;

a second insulating layer over the oxide insulating layer and the electrode layer; and

a pixel electrode over the second insulating layer and electrically connected to the electrode layer,

wherein the oxide insulating layer is in contact with a side surface of the oxide semiconductor film,

wherein the second insulating layer is in contact with a second region the oxide semiconductor film, and

wherein the second region is between the first region and a channel formation region of the oxide semiconductor film.

19. The semiconductor device according to claim 18, wherein the first and the second regions overlap the gate electrode layer.

20. The semiconductor device according to claim 18, wherein the electrode layer is in contact with the first region of the oxide semiconductor film through an opening in the oxide insulating layer.