Two-terminal reversibly switchable memory device

• US 10,680,171 B2
• Filed: 01/30/2019
• Issued: 06/09/2020
• Est. Priority Date: 02/06/2004
• Status: Active Grant

• Current Assignee: Hefei Reliance Memory Limited
• Original Assignee: Hefei Reliance Memory Limited
• Inventors: Rinerson, Darrell, Chevallier, Christophe J., Kinney, Wayne, Lambertson, Roy, Sanchez, Jr., John E., Schloss, Lawrence, Swab, Philip, Ward, Edmond
• Primary Examiner(s): Fan, Bo
• Application Number:
  US16/262,841
• Publication Number:
  US 20190173006A1
• Time in Patent Office: 496 Days
• Field of Search: 257 4, 257 35, 257 43, 365185
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0009 RRAM elements whose operation depends upon chemical change
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/005 Read using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/11 Metal ion trapping, i.e. using memory material including cavities, pores or spaces in form of tunnels or channels wherein metal ions can be trapped but do not react and form an electro-deposit creating filaments or dendrites
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/53 Structure wherein the resistive material being in a transistor, e.g. gate
• CPC Class Codes: G11C 2213/54 Structure including a tunneling barrier layer, the memory effect implying the modification of tunnel barrier conductivity
• CPC Class Codes: G11C 2213/56 Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/24 : based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 : the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/828 : Current flow limiting means within the switching material region, e.g. constrictions
• CPC Class Codes: H10N 70/841 : Electrodes
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

Claims

1. A two-terminal memory cell comprising:

a mixed valence oxide;

a mixed electronic ionic conductor coupled with the mixed valence oxide;

a first memory electrode in contact with the mixed valence oxide; and

a second memory electrode coupled with the mixed electronic ionic conductor.

2. The two-terminal memory cell of claim 1, wherein:

the mixed electronic ionic conductor is uniform in conduction.

3. The two-terminal memory cell of claim 1, wherein:

the mixed electronic ionic conductor is lacking in uniformity in conduction.

4. The two-terminal memory cell of claim 3, wherein:

the uniformity of the mixed electronic ionic conductor varies in a direction from the mixed valence oxide to the second memory electrode.

5. The two-terminal memory cell of claim 3, wherein:

the uniformity of the mixed electronic ionic conductor varies in a direction orthogonal to a direction from the mixed valence oxide to the second memory electrode.

6. The two-terminal memory cell of claim 1, wherein:

the mixed valence oxide is uniform in oxidation.

7. The two-terminal memory cell of claim 1, wherein:

the mixed valence oxide is lacking in uniformity in oxidation.

8. The two-terminal memory cell of claim 7, wherein:

the uniformity of the mixed valence oxide varies in a direction from the mixed electronic ionic conductor to the first memory electrode.

9. The two-terminal memory cell of claim 8, wherein:

the uniformity of the mixed valence oxide varies in a direction orthogonal to a direction from the mixed electronic ionic conductor to the first memory electrode.

10. The two-terminal memory cell of claim 1, wherein the mixed valence oxide is crystalline.

11. A three-terminal memory cell comprising:

a memory element comprising;

a mixed valence oxide, and

a mixed electronic ionic conductor coupled with the mixed valence oxide;

a gate memory electrode coupled with the mixed valence oxide;

a source memory electrode coupled with the memory element; and

a drain memory electrode coupled with the memory element.

12. The three-terminal memory cell of claim 11, wherein:

the mixed electronic ionic conductor is uniform in conduction.

13. The three-terminal memory cell of claim 11, wherein:

the mixed electronic ionic conductor is lacking in uniformity in conduction.

14. The three-terminal memory cell of claim 13, wherein:

the uniformity of the mixed electronic ionic conductor varies in a direction from the mixed valence oxide to at least one of the source memory electrode and the drain memory electrode.

15. The three-terminal memory cell of claim 13, wherein:

the uniformity of the mixed electronic ionic conductor varies in a direction orthogonal to a direction from the mixed valence oxide to at least one of the source memory electrode and the drain memory electrode.

16. The three-terminal memory cell of claim 11, wherein:

the mixed valence oxide is uniform in oxidation.

17. The three-terminal memory cell of claim 11, wherein:

the mixed valence oxide is lacking in uniformity in oxidation.

18. The three-terminal memory cell of claim 17, wherein:

the uniformity of the mixed valence oxide varies in a direction from the mixed electronic ionic conductor to the gate memory electrode.

19. The three-terminal memory cell of claim 17, wherein:

the uniformity of the mixed valence oxide varies in a direction orthogonal to a direction from the mixed electronic ionic conductor to the gate memory electrode.

20. The three-terminal memory cell of claim 11, wherein the mixed valence oxide is crystalline.