Multi-level inverter

• US 10,680,506 B2
• Filed: 06/24/2019
• Issued: 06/09/2020
• Est. Priority Date: 03/26/2014
• Status: Active Grant

• Current Assignee: Solaredge Technologies Incorporated
• Original Assignee: Solaredge Technologies Incorporated
• Inventors: Yoscovich, Ilan, Glovinsky, Tzachi, Sella, Guy, Galin, Yoav
• Primary Examiner(s): Zhang, Jue
• Assistant Examiner(s): Jackson, Lakaisha
• Application Number:
  US16/450,635
• Publication Number:
  US 20190312500A1
• Time in Patent Office: 351 Days
• CPC Class Codes: H02M 1/0054 Transistor switching losses periodically suspending operation of switching converter in low power mode H02M1/0035
• CPC Class Codes: H02M 1/0095 Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/126 using passive filters
• CPC Class Codes: H02M 1/143 using compensating arrangements for reducing noise from the supply in transmission systems H04B15/005
• CPC Class Codes: H02M 7/483 Converters with outputs that each can have more than two voltages levels
• CPC Class Codes: H02M 7/4833 Capacitor voltage balancing
• CPC Class Codes: H02M 7/4835 comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
• CPC Class Codes: H02M 7/4837 Flying capacitor converters
• CPC Class Codes: H02M 7/537 using semiconductor devices only, e.g. single switched pulse inverters

Abstract

A multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.

Claims

1. An apparatus comprising:

first and second direct-current (DC) terminals configured to receive a DC voltage;

a first phase block including a first pair of input terminals and a first alternating-current (AC) terminal;

a second phase block including a second pair of input terminals and a second AC terminal, wherein the first and the second AC terminals are configured to output a single phase sine wave voltage at a first frequency; and

an interphase circuit including an intersection point, wherein the interphase circuit is configured to;

periodically at the first frequency, during a first half-cycle of each of a plurality of cycles of the single phase sine wave voltage, connect the first pair of input terminals between the first DC terminal and the intersection point, and the second pair of input terminals between the intersection point and the second DC terminal; and

periodically at the first frequency, during a second half-cycle of each of the plurality of cycles of the single phase sine wave voltage, connect the second pair of input terminals between the first DC terminal and the intersection point, and the first pair of input terminals between the intersection point and the second DC terminal.

2. The apparatus of claim 1, wherein:

the first phase block is configured to generate a first sine wave voltage at the first frequency and at a first phase on the first AC terminal;

the second phase block is configured to generate a second sine wave voltage at the first frequency and at a second phase on the second AC terminal;

the first phase and the second phase are 180 degrees phase shifted from each other; and

the single phase sine wave voltage is formed as a difference between the first and the second sine wave voltages.

3. The apparatus of claim 1, wherein the interphase circuit is configured to conduct current between the first phase block and the intersection point, and between the second phase block and the intersection point, such that ripple voltage at the first frequency is removed across the first pair of input terminals and removed across the second pair of input terminals.

4. The apparatus of claim 3, wherein:

the first and the second phase blocks are configured to operate at a second frequency that is greater than the first frequency; and

the interphase circuit is configured to filter current at the second frequency from flowing between the first and the second phase blocks through the intersection point.

5. The apparatus of claim 1, wherein the first and the second phase blocks each comprise one of a flying capacitor circuit, a half-bridge circuit, or a DC-to-DC converter.

6. The apparatus of claim 5, further comprising a controller circuit;

wherein the first phase block comprises a first plurality of switches, the second phase block comprises a second plurality of switches, and the first plurality of switches corresponds one-to-one with the second plurality of switches; and

wherein the controller circuit is configured to switch, at a second frequency that is greater than the first frequency, the first plurality of switches and the second plurality of switches such that each switch of the first plurality of switches is turned on and off substantially complementary to its corresponding switch in the second plurality of switches.

7. The apparatus of claim 5, wherein:

the first and the second phase blocks are configured to operate at a second frequency that is greater than the first frequency and that is greater than 16 kHz; and

the first frequency is 50 Hz or 60 Hz.

8. The apparatus of claim 1, further comprising one or more first capacitors connected between the first DC terminal and the intersection point, and one or more second capacitors connected between the second DC terminal and the intersection point.

9. The apparatus of claim 1, wherein the interphase circuit comprises:

a first plurality of switches configured to connect, during the first half-cycle of each of the plurality of cycles, the first pair of input terminals between the first DC terminal and the intersection point, and the second pair of input terminals between the intersection point and the second DC terminal; and

a second plurality of switches configured to connect, during the second half-cycle of each of the plurality of cycles, the second pair of input terminals between the first DC terminal and the intersection point, and the first pair of input terminals between the intersection point and the second DC terminal.

10. The apparatus of claim 9, wherein the first plurality of switches is configured to turn on and off substantially complimentary to the second plurality of switches.

11. The apparatus of claim 10, wherein the first plurality of switches is configured to turn on and off substantially complimentary to the second plurality of switches such that the first plurality of switches is configured to turn on and off with mutual dead time to the second plurality of switches.

12. The apparatus of claim 9, wherein:

each of the first plurality of switches is configured to close during the first half-cycle of each of the plurality of cycles, and open during the second half-cycle of each of the plurality of cycles, according to a first control signal; and

each of the second plurality of switches is configured to open during the first half-cycle of each of the plurality of cycles, and close during the second half-cycle of each of the plurality of cycles, according to a second control signal.

13. The apparatus of claim 9, wherein during the plurality of cycles, the first plurality of switches are configured to be open whenever the second plurality of switches are closed, and the second plurality of switches are configured to be open whenever the first plurality of switches are closed.

14. The apparatus of claim 1, wherein

the first phase block is configured to generate a first pulse width modulated voltage waveform at a second frequency, and to filter the first pulse width modulated voltage waveform to produce a first sine wave voltage at the first frequency;

the second phase block is configured to generate a second pulse width modulated voltage waveform at the second frequency, and to filter the second pulse width modulated voltage waveform to produce a second sine wave voltage at the first frequency;

the second frequency is greater than the first frequency; and

the single phase sine wave voltage is a difference between the first sine wave voltage and the second sine wave voltage.

15. The apparatus of claim 14, wherein the second frequency is greater than 16 kHz.

16. A method comprising:

converting a direct-current (DC) voltage across first and second DC terminals to a single phase sine wave voltage at a first frequency across first and second alternating-current (AC) terminals using;

a first phase block having a first pair of input terminals and the first AC terminal, a second phase block having a second pair of input terminals and the second AC terminal, and an interphase circuit having an intersection point, wherein the converting comprises;

a) periodically at the first frequency, during a first half-cycle of each of a plurality of cycles of the single phase sine wave voltage, connecting the first pair of input terminals between the first DC terminal and the intersection point, and the second pair of input terminals between the intersection point and the second DC terminal; and

b) periodically at the first frequency, during a second half-cycle of each of the plurality of cycles of the single phase sine wave voltage, connecting the second pair of input terminals between the first DC terminal and the intersection point, and the first pair of input terminals between the intersection point and the second DC terminal.

17. The method of claim 16, further comprising:

generating, with the first phase block, a first sine wave voltage at the first frequency and at a first phase on the first AC terminal; and

generating, with the second phase block, a second sine wave voltage at the first frequency and at a second phase on the second AC terminal;

wherein the first phase and the second phase are 180 degrees phase shifted from each other, and the single phase sine wave voltage is formed as a difference between the first and the second sine wave voltages.

18. The method of claim 16, further comprising conducting, via the interphase circuit, current between the first phase block and the intersection point, and between the second phase block and the intersection point, such that ripple voltage at the first frequency is removed across the first pair of input terminals and removed across the second pair of input terminals.

19. The method of claim 18, further comprising:

operating the first and the second phase blocks at a second frequency that is greater than the first frequency; and

filtering, with the interphase circuit, current at the second frequency from flowing between the first and the second phase blocks through the intersection point.

20. The method of claim 16, wherein the first and the second phase blocks each comprise one of a flying capacitor circuit, a half-bridge circuit, or a DC-to-DC converter.

21. The method of claim 20, further comprising:

switching, at a second frequency that is greater than the first frequency, a first plurality of switches in the first phase block and a second plurality of switches in the second phase block;

wherein the first plurality of switches corresponds one-to-one with the second plurality of switches, and each switch of the first plurality of switches is turned on and off substantially complementary to its corresponding switch in the second plurality of switches.

22. The method of claim 20, further comprising operating the first and the second phase blocks at a second frequency that is greater than the first frequency and that is greater than 16 kHz, wherein the first frequency is 50 Hz or 60 Hz.

23. The method of claim 16, wherein the interphase circuit comprises one or more first capacitors connected between the first DC terminal and the intersection point, and one or more second capacitors connected between the second DC terminal and the intersection point.

24. The method of claim 16, further comprising:

controlling a first plurality of switches to connect, during the first half-cycle of each of the plurality of cycles, the first pair of input terminals between the first DC terminal and the intersection point, and the second pair of input terminals between the intersection point and the second DC terminal; and

controlling a second plurality of switches to connect, during the second half-cycle of each of the plurality of cycles, the second pair of input terminals between the first DC terminal and the intersection point, and the first pair of input terminals between the intersection point and the second DC terminal.

25. The method of claim 24, further comprising turning on and off, at the first frequency, the first plurality of switches substantially complimentary to turning on and off the second plurality of switches.

26. The method of claim 25, further comprising turning on and off, at the first frequency, the first plurality of switches substantially complimentary to turning on and off the second plurality of switches such that the first plurality of switches is switched with mutual dead time to the second plurality of switches.

27. The method of claim 24, further comprising:

closing the first plurality of switches during the first half-cycle of each of the plurality of cycles, and opening the first plurality of switches during the second half-cycle of each of the plurality of cycles, according to a first control signal; and

opening the second plurality of switches during the first half-cycle of each of the plurality of cycles, and closing the second plurality of switches during the second half-cycle of each of the plurality of cycles, according to a second control signal.

28. The method of claim 24, further comprising:

opening, during the plurality of cycles, the first plurality of switches whenever the second plurality of switches are closed; and

opening, during the plurality of cycles, the second plurality of switches whenever the first plurality of switches are closed.

29. The method of claim 16, further comprising:

generating, with the first phase block, a first pulse width modulated voltage waveform at a second frequency that is greater than the first frequency;

generating, with the second phase block, a second pulse width modulated voltage waveform at the second frequency;

filtering the first pulse width modulated voltage waveform to produce a first sine wave voltage at the first frequency; and

filtering the second pulse width modulated voltage waveform to produce a second sine wave voltage at the first frequency;

wherein the single phase sine wave voltage is a difference between the first sine wave voltage and the second sine wave voltage.

30. The method of claim 29, wherein the second frequency is greater than 16 kHz.