Envelope tracking system for transmitting a wide modulation bandwidth signal(s)

• US 10,680,559 B2
• Filed: 02/05/2018
• Issued: 06/09/2020
• Est. Priority Date: 10/06/2017
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Khlat, Nadim, Folkmann, Andrew F.
• Primary Examiner(s): Tayong, Helene E
• Application Number:
  US15/888,300
• Publication Number:
  US 20190109613A1
• Time in Patent Office: 855 Days
• Field of Search: 375219
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0233 by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence
• CPC Class Codes: H03F 2200/105 A non-specified detector of the power of a signal being used in an amplifying circuit
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2201/3215 To increase the output power or efficiency
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 2001/0408 with power amplifiers
• CPC Class Codes: H04B 2001/0425 with linearisation using predistortion
• CPC Class Codes: H04L 69/04 Protocols for data compression, e.g. ROHC
• CPC Class Codes: H04W 28/06 Optimizing the usage of the radio link, e.g. header compression, information sizing , discarding information system modifying transmission characteristic according to link quality by modifying frame length H04L1/0007; dynamic adaptation of the packet size for flow control or congestion control H04L47/365
• CPC Class Codes: H04W 52/0209 in terminal devices terminal devices per se H04W88/02
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

An envelope tracking (ET) system is provided. The ET amplifies a radio frequency (RF) signal correspond to an amplitude bandwidth exceeding a voltage modulation bandwidth limitation of the ET system. The ET system compresses the amplitude bandwidth to match the voltage modulation bandwidth of the ET system. More specifically, the ET system compresses a predefined voltage waveform, which tracks time-variant amplitudes of a digital form of the RF signal, to generate a modified voltage waveform at a reduced bandwidth. To ensure that signal distortion(s) resulted from the bandwidth compression can be corrected, the ET system nonlinearly modifies predefined amplitude(s) of the predefined voltage waveform to generate modified amplitude(s) of the modified voltage waveform that is never less than the predefined amplitude(s) of the predefined voltage waveform. As such, the ET system can amplify the RF signal with improved linearity and efficiency, without degrading spectral performance of the RF signal.

Claims

1. An envelope tracking (ET) system, comprising:

a signal input configured to receive a digital signal corresponding to a signal modulation bandwidth;

a voltage output configured to output a digital voltage signal corresponding to a voltage modulation bandwidth less than the signal modulation bandwidth; and

digital voltage processing circuitry configured to;

receive a plurality of signal amplitudes representing a time-variant amplitude envelope of the digital signal;

generate a plurality of predefined voltage amplitudes based on the plurality of signal amplitudes, respectively;

nonlinearly modify the plurality of predefined voltage amplitudes to generate the digital voltage signal comprising a plurality of modified voltage amplitudes consistently greater than or equal to the plurality of predefined voltage amplitudes, respectively;

perform memory digital pre-distortion (mDPD) on the digital voltage signal; and

provide the digital voltage signal to the voltage output.

2. The ET system of claim 1 wherein the digital voltage processing circuitry is further configured to generate a plurality of voltage differential amplitudes indicating amplitude differentials between the plurality of modified voltage amplitudes and the plurality of predefined voltage amplitudes, respectively.

3. The ET system of claim 2 wherein the digital voltage processing circuitry comprises:

voltage look-up table (LUT) circuitry coupled to the signal input and configured to;

receive the plurality of signal amplitudes from the signal input; and

generate the plurality of predefined voltage amplitudes based on the plurality of signal amplitudes, respectively;

a nonlinear bandwidth compression circuit coupled to the voltage LUT circuitry and configured to;

receive the plurality of predefined voltage amplitudes from the voltage LUT circuitry; and

nonlinearly modify the plurality of predefined voltage amplitudes to generate the digital voltage signal comprising the plurality of modified voltage amplitudes greater than or equal to the plurality of predefined voltage amplitudes, respectively;

voltage signal delay circuitry coupled to the voltage LUT circuitry and configured to delay the plurality of predefined voltage amplitudes by a defined delay to generate a plurality of delayed predefined voltage amplitudes, respectively; and

voltage combiner circuitry coupled to the nonlinear bandwidth compression circuit and the voltage signal delay circuitry, the voltage combiner circuitry configured to combine the plurality of modified voltage amplitudes and the plurality of delayed predefined voltage amplitudes to generate the plurality of voltage differential amplitudes, respectively.

4. The ET system of claim 3 wherein the nonlinear bandwidth compression circuit comprises:

an input node, an output node, and a reference node;

a delay path provided between the input node and the reference node;

control circuitry comprising;

a reference input interface coupled to the reference node;

an output interface coupled to the output node;

one or more input interfaces; and

a feedback interface;

one or more combiners provided in parallel between the delay path and the one or more input interfaces in the control circuitry, respectively; and

feedback circuitry provided between the output interface and the feedback interface.

5. The ET system of claim 4 wherein:

the delay path comprises one or more delay circuits provided in series between the input node and the reference node and configured to generate one or more delta delays, respectively; and

the defined delay of the delay path equals approximately a sum of the one or more delta delays.

6. The ET system of claim 5 wherein:

the one or more delay circuits comprise one or more input ends and one or more output ends, respectively; and

the one or more combiners are provided in parallel between the one or more input ends and the one or more input interfaces, respectively.

7. The ET system of claim 3 further comprising mDPD circuitry coupled to the nonlinear bandwidth compression circuit and configured to perform the mDPD on the digital voltage signal.

8. The ET system of claim 3 wherein the defined delay equals an inherent processing delay of the nonlinear bandwidth compression circuit.

9. The ET system of claim 3 further comprising:

digital signal processing circuitry configured to;

receive the plurality of signal amplitudes from the signal input;

receive the plurality of voltage differential amplitudes from the digital voltage processing circuitry; and

perform digital pre-distortion (DPD) on the digital signal based on the plurality of signal amplitudes and the plurality of voltage differential amplitudes to generate a pre-distorted digital signal comprising a plurality of pre-distorted signal amplitudes, respectively; and

a signal output configured to receive and output the pre-distorted digital signal.

10. The ET system of claim 9 wherein the digital signal processing circuitry comprises:

amplitude delay circuitry configured to delay the plurality of signal amplitudes in the digital signal by the defined delay to generate a plurality of delayed signal amplitudes; and

DPD circuitry configured to digitally pre-distort the digital signal based on the plurality of voltage differential amplitudes and the plurality of delayed signal amplitudes.

11. The ET system of claim 9 wherein the digital signal processing circuitry further comprises:

digital splitter circuitry configured to receive and split the digital signal into a digital in-phase signal comprising a plurality of in-phase signal amplitudes and a digital quadrature signal each comprising a plurality of quadrature signal amplitudes; and

in-phase/quadrature (I/Q) DPD circuitry configured to digitally pre-distort the digital in-phase signal and the digital quadrature signal to generate a pre-distorted digital in-phase signal and a pre-distorted digital quadrature signal, respectively.

12. The ET system of claim 9 further comprising:

a voltage digital-to-analog converter (DAC) coupled to the voltage output and configured to convert the digital voltage signal into a target voltage signal having a time-variant voltage envelope corresponding to the plurality of modified voltage amplitudes; and

a signal DAC coupled to the signal output and configured to convert the pre-distorted digital signal into a radio frequency (RF) signal.

13. The ET system of claim 12 further comprising:

tracker circuitry coupled to the voltage DAC and configured to receive the target voltage signal and generate an ET modulated voltage tracking the time-variant voltage envelope of the target voltage signal; and

at least one amplifier circuit configured to;

receive the RF signal from the signal DAC;

receive the ET modulated voltage from the tracker circuitry; and

amplify the RF signal based on the ET modulated voltage.

14. A transceiver circuit comprising:

a signal input configured to receive a digital signal corresponding to a signal modulation bandwidth;

a voltage output configured to output a digital voltage signal corresponding to a voltage modulation bandwidth less than the signal modulation bandwidth;

digital voltage processing circuitry configured to;

receive a plurality of signal amplitudes representing a time-variant amplitude envelope of the digital signal from the signal input;

generate a plurality of predefined voltage amplitudes based on the plurality of signal amplitudes, respectively;

nonlinearly modify the plurality of predefined voltage amplitudes to generate the digital voltage signal comprising a plurality of modified voltage amplitudes greater than or equal to the plurality of predefined voltage amplitudes, respectively;

provide the digital voltage signal to the voltage output; and

generate a plurality of voltage differential amplitudes indicating amplitude differentials between the plurality of modified voltage amplitudes and the plurality of predefined voltage amplitudes, respectively; and

digital signal processing circuitry configured to;

receive the plurality of signal amplitudes from the signal input;

receive the plurality of voltage differential amplitudes from the digital voltage processing circuitry;

perform digital pre-distortion (DPD) on the plurality of signal amplitudes and the plurality of voltage differential amplitudes to generated a pre-distorted digital signal comprising a plurality of pre-distorted signal amplitudes, respectively; and

a signal output configured to receive and output the pre-distorted digital signal.

15. The transceiver circuit of claim 14 wherein the digital voltage processing circuitry comprises:

voltage look-up table (LUT) circuitry coupled to the signal input and configured to;

receive the plurality of signal amplitudes from the signal input; and

generate the plurality of predefined voltage amplitudes based on the plurality of signal amplitudes, respectively;

a nonlinear bandwidth compression circuit coupled to the voltage LUT circuitry and configured to;

receive the plurality of predefined voltage amplitudes from the voltage LUT circuitry; and

nonlinearly modify the plurality of predefined voltage amplitudes to generate the digital voltage signal comprising the plurality of modified voltage amplitudes greater than or equal to the plurality of predefined voltage amplitudes, respectively;

voltage signal delay circuitry coupled to the voltage LUT circuitry and configured to delay the plurality of predefined voltage amplitudes by a defined delay to generate a plurality of delayed predefined voltage amplitudes, respectively; and

voltage combiner circuitry coupled to the nonlinear bandwidth compression circuit and the voltage signal delay circuitry, the voltage combiner circuitry configured to combine the plurality of modified voltage amplitudes and the plurality of delayed predefined voltage amplitudes to generate the plurality of voltage differential amplitudes, respectively.

16. The transceiver circuit of claim 15 wherein the nonlinear bandwidth compression circuit comprises:

an input node, an output node, and a reference node;

a delay path provided between the input node and the reference node;

control circuitry comprising;

a reference input interface coupled to the reference node;

an output interface coupled to the output node;

one or more input interfaces; and

a feedback interface;

one or more combiners provided in parallel between the delay path and the one or more input interfaces in the control circuitry, respectively; and

feedback circuitry provided between the output interface and the feedback interface.

17. The transceiver circuit of claim 16 wherein:

the delay path comprises one or more delay circuits provided in series between the input node and the reference node and configured to generate one or more delta delays, respectively; and

the defined delay of the delay path equals approximately a sum of the one or more delta delays.

18. The transceiver circuit of claim 17 wherein:

the one or more delay circuits comprise one or more input ends and one or more output ends, respectively; and

the one or more combiners are provided in parallel between the one or more input ends and the one or more input interfaces, respectively.

19. The transceiver circuit of claim 15 wherein the digital signal processing circuitry comprises:

amplitude delay circuitry configured to delay the plurality of signal amplitudes in the digital signal by the defined delay to generate a plurality of delayed signal amplitudes; and

DPD circuitry configured to digitally pre-distort the digital signal based on the plurality of voltage differential amplitudes and the plurality of delayed signal amplitudes.

20. The transceiver circuit of claim 19 wherein the digital signal processing circuitry further comprises:

digital splitter circuitry configured to receive and split the digital signal into a digital in-phase signal comprising a plurality of in-phase signal amplitudes and a digital quadrature signal each comprising a plurality of quadrature signal amplitudes; and

in-phase/quadrature (I/Q) DPD circuitry configured to digitally pre-distort the digital in-phase signal and the digital quadrature signal to generate a pre-distorted digital in-phase signal and a pre-distorted digital quadrature signal, respectively.