Quadrature clock correction circuit for transmitters
First Claim
1. A transmitter, comprising:
- a multiplexer circuit configured to serialize an input signal to generate an output signal based on a four-phase clock signal;
first and second clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of the four-phase clock signal;
third and fourth clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal, wherein the first, second, third and fourth clock correction circuits are each separate circuits;
a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and
a calibration circuit configured to supply first and second control signals to each of the first and second clock correction circuits, and third and fourth control signals to each of the third and fourth clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.
1 Assignment
0 Petitions
Accused Products
Abstract
A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.
31 Citations
20 Claims
-
1. A transmitter, comprising:
-
a multiplexer circuit configured to serialize an input signal to generate an output signal based on a four-phase clock signal; first and second clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of the four-phase clock signal; third and fourth clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal, wherein the first, second, third and fourth clock correction circuits are each separate circuits; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply first and second control signals to each of the first and second clock correction circuits, and third and fourth control signals to each of the third and fourth clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A method of clock correction in a transmitter, comprising:
-
outputting in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal from first and second clock correction circuits; outputting quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal from third and fourth clock correction circuits, wherein the first, second, third and fourth clock correction circuits are each separate circuits; detecting, at a detector circuit, duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; providing first and second control signals to each of the first and second clock correction circuits, and third and fourth control signals to each of the third and fourth clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit. - View Dependent Claims (11, 12, 13, 14)
-
-
15. A quadrature clock correction (QCC) circuit, comprising:
-
first and second clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; third and fourth clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of a four-phase clock signal, wherein the first, second, third and fourth clock correction circuits are each separate circuits; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply first and second control signals to each of the first and second clock correction circuits, and third and fourth control signals to each of the third and fourth clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification