Replication in a protocol offload network interface controller

• US 10,681,145 B1
• Filed: 12/22/2014
• Issued: 06/09/2020
• Est. Priority Date: 12/22/2014
• Status: Active Grant

• Current Assignee: Chelsio Communications Incorporated
• Original Assignee: Chelsio Communications Incorporated
• Inventors: Eiriksson, Asgeir Thor
• Primary Examiner(s): Won, Michael
• Application Number:
  US14/580,117
• Time in Patent Office: 1,996 Days
• Field of Search: 709230
• CPC Class Codes: H04L 67/1095 Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes
• CPC Class Codes: H04L 67/142 Managing session states for stateless protocols; Signalling session states; State transitions; Keeping-state mechanisms
• CPC Class Codes: H04L 67/2866 Architectures; Arrangements
• CPC Class Codes: H04L 67/59 Providing operational support to end devices by off-loading in the network or by emulation, e.g. when they are unavailable
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/40 for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection management of faults, events, alarms or notifications in data switching networks H04L41/06

Abstract

Data replication can be supported efficiently in a protocol offload device (such as a protocol offload device to offload transport layer protocol processing from a host) by supporting a shared memory (SHM) abstraction for the send and receive buffers that are used in protocol offload devices. The protocol offload send and receive buffers are accessed using a per offloaded connection virtual address method that maps transport protocol sequence numbers (such as TCP protocol sequence numbers), to memory locations within buffers, and, for example, either page tables and paged memory or segment tables and segmented memory tables are used to access the memory.

Claims

1. Network interface circuitry, configured to couple a host computer and a network, the network interface circuitry comprising at least one processor configured to:

offload from the host computer at least a portion of transport layer communication protocol processing to accomplish at least two separate stateful transport layer communication connections, each between the host computer and a peer, wherein the two separate stateful layer communication connections are between the host and two separate peers; and

access at least one data item originating from the host;

wherein the at least a portion of transport layer communication protocol processing by the network interface circuitry includes replicating the accessed at least one data item to generate a plurality of replicated data items and providing each of the plurality of replicated data items from the network interface circuitry using a separate one of the at least two separate stateful transport layer communication connections, and

wherein when the plurality of replicated data items are provided from the network interface circuitry using the at least two separate stateful transport layer communication connections, maintain a single data structure to indicate a state of all of the at least two separate stateful transport layer communication connections.

2. The network interface circuitry of claim 1, wherein:

at least one of the stateful transport layer communication connections is to a peer residing on the host.

3. The network interface circuitry of claim 1, wherein:

at least one of the stateful transport layer communication connections is to a peer residing across the network.

4. The network interface circuitry of claim 1, wherein the network interface circuitry is configured to receive from the host computer the at least one data item and an indication of the at least two separate stateful transport layer communication connections.

5. The network interface circuitry of claim 4, wherein:

the received indication of the at least two separate stateful transport layer communication connections is a proxy for, what appears to the host to be, a single stateful transport layer communication connection, wherein a mapping of the at least two separate stateful transport layer communication connections to the received indication is maintained by the network interface circuitry.

6. The network interface circuitry of claim 1, wherein:

the processor is configured to operate the transport layer communication protocol processing offload at least in part according to transport layer communication connection states maintained in a memory accessible by transport layer communication protocol processing offload operation, including accessing each transport layer communication connection state in the memory using the access procedure, to access that transport layer communication connection state in the memory according to an identifier corresponding to that transport layer communication connection state.

7. The network interface circuitry of claim 1, wherein:

the processor is configured to provide information regarding the reliability at which the plurality of replicated data items have been transmitted via the at least two separate stateful transport layer communication connections.

8. The network interface circuitry of claim 7, wherein:

the processor being configured to provide information regarding the reliability at which the plurality of replicated data items have been transmitted via the at least two separate stateful transport layer communication connections includes the processor being configured to provide the information to the host.

9. The network interface circuitry of claim 7, wherein:

the processor being configured to provide information regarding the reliability at which the plurality of replicated data items have been transmitted via the at least two separate stateful transport layer communication connections includes the processor being configured to provide the information to control plane processing of the network interface circuitry.

10. The network interface circuitry of claim 7, wherein:

the processor being configured to provide information regarding the reliability at which the plurality of replicated data items have been transmitted via the at least two separate stateful transport layer communication connections includes the processor being configured to provide the information to both the host and to the control plane processing of the network interface circuitry.

11. The network interface circuitry of claim 7, wherein:

the processor being configured to provide information regarding the reliability at which the plurality of replicated data items have been transmitted via the at least two separate stateful transport layer connections includes the processor being configured to provide information that the plurality of replicated data items were not successfully transmitted via the at least two separate stateful transport layer communication connections.

12. The network interface circuitry of claim 7, wherein:

the processor is configured to maintain a reference count of a number of the at least two stateful transport layer communication connections; and

the processor is further configured to adjust the reference count based on the at least two separate stateful transport layer communication connections successfully transmitting the plurality of replicated data items,

the processor providing the collective notification upon the reference count indicating that the plurality of replicated data items have been reliably transmitted via all of the at least two separate stateful transport layer communication connections.

13. The network interface circuitry of claim 12, wherein:

the collective notification to the host includes releasing space in a memory into which the host provided the plurality of replicated data items.

14. The network interface circuitry of claim 1, wherein:

at least one data item originating from the host is stored in a memory accessible by the transport layer communication protocol processing offload operation.

15. The network interface circuitry of claim 14, wherein:

the transport layer communication protocol processing offload operation for each of the at least two separate stateful transport layer communication connections includes adjusting a pointer for that stateful transport layer communication connection according to transmission of one of the plurality of replicated data items by the network interface circuitry, via that stateful transport layer communication connection.

16. The network interface circuitry of claim 15, wherein:

adjusting a pointer for that stateful transport layer connection includes adjusting the pointer based on a change in transmission sequence number for that stateful transport layer communication connection.

17. The network interface circuitry of claim 1, configured such that:

the plurality of replicated data items originating from the host are looped around to be received data on at least one other stateful transport layer communication connection, of the at least two stateful communication connections, with the host.