Receive-side scaling for wireless communication devices

• US 10,681,607 B2
• Filed: 06/22/2018
• Issued: 06/09/2020
• Est. Priority Date: 06/22/2018
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Nirav, Dalai, Pabitra, Soussi, El-Houari, Van Ee, Rene, Deuskar, Gaurish
• Primary Examiner(s): Nguyen, Phuongchau Ba
• Application Number:
  US16/016,118
• Publication Number:
  US 20190045421A1
• Time in Patent Office: 718 Days
• Field of Search: 370351, 370368, 370249, 370250, 370252, 370253, 370360, 370377, 370386, 370389, 370394, 3703951, 37039531, 370432, 370465, 370471
• CPC Class Codes: H04L 45/7453 using hashing
• CPC Class Codes: H04L 45/74591 using content-addressable memories [CAM]
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04W 40/02 Communication route or path selection, e.g. power-based or shortest path routing

Abstract

Systems, methods, and computer-readable storage media for an enhanced RSS (eRSS) mechanisms are provided. The eRSS mechanisms may involve routing received data packets to application processor cores based on network-specific identifier(s), such as an Evolved Packet System (EPS) bearer identity (ID), a Packet Data Network (PDN) ID, an Access Point Name (APN), or a Quality of Service (QoS) Flow Identifier (QFI). The network-specific IDs may be located in a layer 2 (L2) protocol stack, which may be stored in cache for use by different layers in the L2 protocol stack. In this way, the network-specific IDs may be readily available for use by the eRSS mechanism, which may improve cache efficiency and reduce storage overhead. Other embodiments may be described and/or claimed.

Claims

1. A system on chip (SoC) for wireless communication modulation and demodulation, the SoC comprising:

baseband circuitry coupled with in-package memory circuitry, wherein;

the in-package memory circuitry is arranged to store a processor core lookup table (PCLT), wherein the PCLT maps network-specific identifiers (NSIs) to core identifiers (CIDs) of a plurality of NSI-CIS pairs for a plurality of cores of application processor circuitry of a host platform to which the SoC is coupled, the NSIs being identifiers specific to a wireless communication protocol used to communicate data packets, and

the baseband circuitry is arranged to operate an enhanced receive side scaling (eRSS) entity to send a data packet to a processor core of the multi-core application processor circuitry that is associated with a CID obtained from the PCLT based on an NSI of the data packet.

2. The SoC of claim 1, wherein the baseband circuitry is arranged to operate the eRSS entity to:

perform a lookup operation on the PCLT using the NSI of the data packet to obtain the CID of the data packet.

3. The SoC of claim 2, wherein, to perform the lookup operation, the baseband circuitry is arranged to operate the eRSS entity to:

calculate a hash of the NSI to obtain an index; and

use the index to obtain the CID of the data packet.

4. The SoC of claim 1, wherein the baseband circuitry is arranged to operate the eRSS entity to:

extract the NSI of the data packet from the data packet.

5. The SoC of claim 4, wherein, to extract the NSI, the baseband circuitry is arranged to operate the eRSS entity to:

extract the NSI from a Packet Data Convergence Protocol (PDCP) protocol data unit (PDU) header of the data packet.

6. The SoC of claim 1, wherein the in-package memory circuitry comprises a cache memory device, and wherein the baseband circuitry is arranged to operate the eRSS entity to:

identify a descriptor of the data packet from a layer 2 (L2) protocol stack used for processing the data packet; and

retrieve the descriptor from the in-package memory circuitry,

wherein the eRSS entity is located in a PDCP layer of the L2 protocol stack, or the eRSS entity is located above the PDCP layer.

7. The SoC of claim 1, wherein, to send the data packet to the processor core of the multi-core application processor circuitry, the baseband circuitry is arranged to:

control storage of the data packet in a receive (Rx) queue associated with the determined CID, wherein the Rx queue is located in the host platform.

8. The SoC of claim 7, wherein the SoC further comprises interconnect (IX) interface circuitry, and wherein, to control storage of the data packet in the Rx queue, the IX interface circuitry is arranged to:

trigger an interrupt request (IRQ) associated with the Rx queue to notify the processor core associated with the determined CID that the data packet is ready for storage in the Rx queue.

9. The SoC of claim 1, wherein the SoC is to operate as a fourth generation (4G) Long Term Evolution (LTE) modem, and the NSI is an Evolved Packet System (EPS) ID, a Packet Data Network (PDN) ID, an Access Point Name (APN), or a Quality of Service (QoS) Class Identifier (QCI), or wherein the SoC is to operate as a fifth generation (5G) New Radio (NR) modem, and the NSI is a QoS Flow Identifier (QFI) or a Fifth Generation (5G) QoS Identifier (5QI).

10. A system on chip (SoC) for wireless communication modulation and demodulation, the SoC comprising:

baseband circuitry with in-package memory circuitry, the baseband circuitry is arranged to;

control storage of a processor core lookup table (PCLT) in the in-package memory circuitry, wherein the PCLT is to map network-specific identifiers (NSIs) to core identifiers (CIDs) of a plurality of NSI-CIS pairs for a plurality of cores of application processor circuitry of a host platform to which the SoC is coupled, and

operate an enhanced receive side scaling (eRSS) entity to send a data packet to a processor core of the multi-core application processor circuitry that is associated with a CID obtained from the PCLT based on an NSI of the data packet,

wherein the in-package memory circuitry comprises a cache memory device, and the baseband circuitry is arranged to operate the eRSS entity to;

identify a descriptor of the data packet from a layer 2 (L2) protocol stack used for processing the data packet; and

retrieve the descriptor from the in-package memory circuitry,

wherein the eRSS entity is located in a PDCP layer of the L2 protocol stack, or the eRSS entity is located above the PDCP layer.

11. The SoC of claim 10, wherein the SoC is to operate as a fourth generation (4G) Long Term Evolution (LTE) modem, and the NSI is an Evolved Packet System (EPS) ID, a Packet Data Network (PDN) ID, an Access Point Name (APN), or a Quality of Service (QoS) Class Identifier (QCI), or wherein the SoC is to operate as a fifth generation (5G) New Radio (NR) modem, and the NSI is a QoS Flow Identifier (QFI) the SoC further comprises interconnect (IX) interface circuitry, and wherein:

the baseband circuitry is arranged to control storage of the data packet in a receive (Rx) queue associated with the determined CID, wherein the Rx queue is located in the host platform, and

the IX interface circuitry is arranged to trigger an interrupt request (IRQ) associated with the Rx queue to notify the processor core associated with the determined CID that the data packet is ready for storage in the Rx queue.

12. One or more non-transitory computer-readable storage media (NTCRSM) comprising instructions, wherein execution of the instructions by circuitry of a user equipment (UE) is to cause the UE to operate an enhanced receive side scaling (eRSS) entity of the UE to:

extract, from each obtained data packet of a data stream, a network-specific identifier (NSI) of each obtained data packet or an NSI associated with the data stream, the NSI is an identifier specific to a wireless communication protocol used to communicate data packets of the data stream;

perform a lookup operation on an indirection table using the extracted NSI to obtain a CID, wherein the indirection table is to store a plurality of CIDs in association with a corresponding NSI, wherein each CID of the plurality of CIDs corresponds with a processor core of a plurality of processor cores of multi-core processor circuitry; and

control storage of the data packet in a receive (Rx) queue associated with the obtained CID.

13. The one or more NTCRSM of claim 12, wherein, to perform the lookup operation, execution of the instructions is to cause the UE to operate the eRSS entity to:

calculate a hash of the NSI to obtain an index; and

use the index to obtain the CID of the data packet.

14. The one or more NTCRSM of claim 12, wherein, to extract the NSI, execution of the instructions is to cause the UE to operate the eRSS entity to:

identify a descriptor of the data packet from a layer 2 (L2) protocol stack used for processing the data packet; and

retrieve the descriptor from in-package memory circuitry.

15. The one or more NTCRSM of claim 14, wherein the eRSS entity is located in a Packet Data Convergence Protocol (PDCP) layer of the L2 protocol stack, or the eRSS entity is located above the PDCP layer, and wherein, to extract the NSI, execution of the instructions is to cause the UE to operate the eRSS entity to:

extract the NSI from a PDCP protocol data unit (PDU) header of the data packet.

16. The one or more NTCRSM of claim 12, wherein, to control storage of the data packet in the Rx queue, execution of the instructions is to cause the UE to operate the eRSS entity to:

issue a deferred procedure call (DPC) associated with the Rx queue.

17. The one or more NTCRSM of claim 12, wherein, to control storage of the data packet in the Rx queue, execution of the instructions is to cause the UE to operate the eRSS entity to:

trigger an interrupt request (IRQ) associated with the Rx queue to notify the processor core associated with the obtained CID that the data packet is ready for storage in the Rx queue.

18. The one or more NTCRSM of claim 12, wherein the NSI is an Evolved Packet System (EPS) identity, a Packet Data Network (PDN) identity, an Access Point Name (APN), or a Quality of Service (QoS) Class Identifier (QCI), a QoS Flow Identifier (QFI), or a Fifth Generation (5G) QoS Identifier (5QI).

19. A computer system capable of wireless communication, the system comprising:

a host platform comprising multi-core processor circuitry and system memory circuitry; and

modem circuitry coupled with the host platform via an interconnect (IX), wherein the modem circuitry comprises baseband circuitry and in-package memory circuitry, and wherein;

the in-package memory circuitry is arranged to store an enhanced receive side scaling (eRSS) entity, and

the baseband circuitry is arranged to operate the eRSS entity to route data packets to individual cores of the multi-core processor circuitry over the IX based on network-specific identifiers (NSIs) of the data packets, the NSIs being identifiers specific to a wireless communication protocol used to communicate data packets of a data stream.

20. The system of claim 19, wherein the in-package memory circuitry is arranged to store a processor core lookup table (PCLT), wherein the PCLT is to map NSIs to core identifiers (CIDs) of a plurality of NSI-CIS pairs for the individual cores, and the baseband circuitry is arranged to operate the eRSS entity to:

extract, from a data packet received by the baseband circuitry, a NSI of the data packet;

perform a lookup operation on the PCLT using the extracted NSI to obtain a CID; and

send the data packet to a processor core of the multi-core processor circuitry that is associated with the determined CID.

21. The system of claim 20, wherein, to perform the lookup operation, the baseband circuitry is arranged to operate the eRSS entity to:

calculate a hash of the NSI to obtain the CID.

22. The system of claim 20, wherein, to extract the NSI, the baseband circuitry is arranged to operate the eRSS entity to:

identify a descriptor of the data packet from a layer 2 (L2) protocol stack used for processing the data packet; and

retrieve the descriptor from the in-package memory circuitry.

23. The system of claim 20, wherein, to send the data packet to the processor core of the multi-core processor circuitry, the baseband circuitry is arranged to operate the eRSS entity to:

control storage of the data packet in a receive (Rx) queue associated with the determined CID, wherein the Rx queue is located in the host platform.

24. The system of claim 23, wherein, to send the data packet to the Rx queue, the modem circuitry is arranged to:

trigger an interrupt request (IRQ) associated with the Rx queue to notify the processor core associated with the determined CID that the data packet is ready for storage in the Rx queue.

25. The system of claim 19, wherein the modem circuitry is to operate as a fourth generation (4G) Long Term Evolution (LTE) modem, and the NSI is an Evolved Packet System (EPS) ID, a Packet Data Network (PDN) ID, an Access Point Name (APN), or a Quality of Service (QoS) Class Identifier (QCI), or the modem circuitry is to operate as a fifth generation (5G) New Radio (NR) modem, and the NSI is a QoS Flow Identifier (QFI).