Cell bottom node reset in memory array

• US 10,685,694 B2
• Filed: 04/17/2019
• Issued: 06/16/2020
• Est. Priority Date: 08/10/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sakurai, Kiyotake, Matsubara, Yasushi
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US16/387,220
• Publication Number:
  US 20190311757A1
• Time in Patent Office: 426 Days
• Field of Search: None
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2255 Bit-line or column circuits
• CPC Class Codes: G11C 11/2257 Word-line or row circuits
• CPC Class Codes: G11C 11/2259 Cell access
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/2293 Timing circuits or methods
• CPC Class Codes: G11C 11/2297 Power supply circuits
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements

Abstract

Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.

Claims

1. A method, comprising:

applying a zero voltage to a plurality of digit lines coupled with a plurality of memory cells comprising a plurality of cell bottom nodes and a plurality of cell plates, wherein each of the cell bottom nodes is configured to be coupled with a respective digit line of the plurality of digit lines; and

activating, based at least in part on applying the zero voltage, a plurality of word lines to couple the plurality of digit lines to the plurality of cell bottom nodes.

2. The method of claim 1, wherein activating the plurality of word lines resets the plurality of cell bottom nodes to the zero voltage.

3. The method of claim 1, further comprising:

applying a signal to perform a reset operation to the plurality of memory cells, wherein applying the zero voltage to the plurality of digit lines is based at least in part on applying the signal.

4. The method of claim 3, wherein:

the signal and the zero voltage are applied simultaneously; and

the plurality of cell bottom nodes are reset to a zero voltage based at least in part on applying the zero voltage to the plurality of digit lines.

5. The method of claim 1, further comprising:

applying a power signal to the plurality of memory cells to initiate a power-up operation; and

determining a voltage of the plurality of digit lines based at least in part on applying the power signal, wherein applying the zero voltage is based at least in part on determining the voltage of the plurality of digit lines.

6. The method of claim 5, wherein determining the voltage of the plurality of digit lines comprises:

detecting a voltage increase based at least in part on applying the power signal; and

determining that the voltage increase satisfies a threshold value.

7. The method of claim 6, further comprising:

issuing one or more signals in response to detecting that the voltage increase satisfies the threshold value, wherein the plurality of word lines are activated based at least in part on issuing the one or more signals.

8. The method of claim 1, further comprising:

activating a switching component coupled with a voltage source and a plurality of equalize lines; and

activating the plurality of equalize lines based at least in part on activating the switching component, wherein applying the zero voltage is based at least in part on activating the plurality of equalize lines.

9. The method of claim 1, further comprising:

applying, from a second voltage source, an activation voltage to the plurality of word lines, wherein activating the plurality of word lines is based at least in part on applying the activation voltage;

activating a selection component coupled with the plurality of digit lines and the plurality of cell bottom nodes based at least in part on applying the activation voltage, wherein each of the plurality of digit lines is coupled with a respective cell bottom node of the plurality of cell bottom nodes based at least in part on activating the selection component; and

activating a plurality of equalize lines based at least in part on activating the selection component.

10. The method of claim 1, wherein:

activating the plurality of word lines comprises applying an activation voltage to the plurality of word lines by an external power source.

11. The method of claim 1, further comprising:

applying the zero voltage to each of the plurality of cell plates; and

writing a logic value to each of the plurality of memory cells based at least in part on applying the voltage to each of the plurality of cell plates.

12. The method of claim 1, wherein the plurality of memory cells comprises ferroelectric memory cells.

13. An apparatus, comprising:

a voltage source;

a plurality of memory cells, each memory cell of the plurality comprising;

a cell plate;

a cell bottom node;

a selection component configured to couple the cell bottom node to a digit line; and

a switching component configured to couple the digit line with the voltage source upon an activation of an equalize line.

14. The apparatus of claim 13, further comprising:

a plurality of equalize lines, wherein an activation of each equalize line of the plurality of equalize lines comprises applying a second voltage to the plurality of equalize lines.

15. The apparatus of claim 13, further comprising:

a plurality of word lines, each word line coupled with a respective memory cell;

a reset line coupled with the voltage source; and

a power source, the power source configured to be coupled with the plurality of word lines based at least in part on the voltage being applied to the reset line.

16. The apparatus of claim 15, further comprising:

a voltage level detector coupled with the power source, the voltage level detector configured to detect that a voltage applied from the power source to the plurality of word lines has satisfied a threshold value.

17. The apparatus of claim 15, wherein each cell plate of the plurality of memory cells is coupled with the voltage source.

18. An apparatus, comprising:

a voltage source;

a plurality of memory cells, wherein each memory cell of the plurality of memory cells comprises a digit line, a cell bottom node, and a cell plate; and

a controller configured to;

apply a voltage from the voltage source to the plurality of digit lines; and

activate a plurality of word lines to couple each of the plurality of digit lines to a respective cell bottom node.

19. The apparatus of claim 18, wherein the controller is configured to:

apply a second voltage to each of the plurality of word lines to reset the cell bottom node in each of the plurality of memory cells.

20. The apparatus of claim 19, wherein the controller is configured to:

receive a signal to perform a reset operation, wherein applying the voltage to the plurality of digit lines and applying the second voltage to the plurality of word lines is based at least in part on receiving the signal.