Semiconductor device

• US 10,685,695 B2
• Filed: 05/07/2019
• Issued: 06/16/2020
• Est. Priority Date: 06/09/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Chang Hoon, Kim, Yong Seok, Lim, Jun Hee
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US16/405,219
• Publication Number:
  US 20190259439A1
• Time in Patent Office: 406 Days
• Field of Search: 365182
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

Claims

1. A semiconductor device comprising:

a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate; and

a peripheral circuit region disposed outside of the memory cell region, and including low voltage transistors and high voltage transistors,

wherein the low voltage transistors have a channel length shorter than a channel length of the high voltage transistors, and

wherein the low voltage transistors include first transistors in which M layers are stacked vertically, and the high voltage transistors include second transistors in which N layers are stacked vertically, M being greater than N, wherein the M lavers have side surfaces substantially coplanar with one another, and the N layers have side surfaces substantially coplanar with one another.

2. The semiconductor device of claim 1, wherein the first transistors include p-type transistors in which A layers are stacked vertically and n-type transistors in which B layers are stacked vertically, A being greater than B.

3. The semiconductor device of claim 1, wherein the first transistors includes a first gate dielectric layer and a first gate electrode layer including C layers, and the second transistors include a second gate dielectric layer and a second gate electrode layer including D layers, and C is greater than D.

4. The semiconductor device of claim 1, wherein the first transistors includes a first gate dielectric layer and a first gate electrode layer including a metal, and

herein the second transistors include a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

5. The semiconductor device of claim 4, wherein the first gate electrode layer includes a first conductive layer including metal and a second conductive layer including polysilicon.

6. The semiconductor device of claim 4, wherein the first transistors further include the. second gate dielectric layer disposed below the first gate dielectric layer.

7. The semiconductor device of claim 6, wherein a thickness of the second gate dielectric layer in the second transistors is greater than a thickness of the second gate dielectric layer in the first transistors.

8. The semiconductor device of claim 4, wherein the first transistors include n-type transistors and p-type transistors, the first gate electrode layer of the n-type, transistors includes a first metal layer, and the first gate electrode layer of the p-type transistors includes a second metal layer having a work function higher than a work function of the first metal layer.

9. The semiconductor device of claim 8, wherein the first gate electrode layer of the p-type transistors further includes the first metal layer on the second metal layer.

10. The semiconductor device of claim 4, wherein the first transistors include n-type transistors and p-type transistors, the first gate electrode layer includes a first conductive layer and a second conductive layer, and a thickness of at least one of the first conductive layer and the second conductive layer is different in the n-type transistors and the p-type transistors.

11. The semiconductor device of claim 4, wherein the first transistors further include the second gate electrode layer stacked on the first gate electrode layer.

12. The semiconductor device of claim 1, wherein the first transistors generate an electrical signal required for communications between the memory cells and an external host, and the second transistors generate an electrical signal required for operations of the memory cells.

13. The semiconductor device of claim 12, wherein the first transistors are included in an input/output circuit.

14. The semiconductor device of claim 1, wherein the low voltage transistors have an operating voltage of 1 V to 5 V, and the high voltage transistors have an operating voltage of 10 V to 40 V.

15. The semiconductor device of claim 1, wherein the memory cells include:

a channel region disposed in the channel holes;

a cell gate dielectric layer including a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and

a cell gate electrode layer surrounding the channel holes.

16. A semiconductor device comprising:

a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate; and

a peripheral circuit region disposed outside of the memory cell region, and including first transistors and second transistors having a channel length longer than a channel length of the first transistors,

wherein the first transistors include a first gate dielectric layer and a first gate electrode layer, and the second transistors include a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer,

wherein the first gate electrode layer includes a first conductive layer including metal and a second conductive layer including polysilicon, and

wherein a thickness of the first gate dielectric law is in a rate of about 30 Å

to about 90 Å

, and a thickness of the second sate dielectric layer is in a range of about 300 Å

to about 500 Å

.

17. The semiconductor device of claim 16, wherein the second gate electrode layer includes polysilicon.

18. The semiconductor device of claim 16. wherein the first gate electrode layer further includes a third conductive layer including metal between the first conductive layer and the second conductive layer.

19. A semiconductor device comprising:

a memory cell region including memory cells including a charge storage layer; and

a peripheral circuit region disposed outside of the memory cell region, and including first transistors including a first gate dielectric layer including a high-k material and a first gate electrode layer, and second transistors including a second gate dielectric layer including silicon dioxide (SiO₂) and a second gate electrode layer including polysilicon,

wherein the first transistors include n-type transistors and p-type transistors, the first gate electrode layer of the p-type transistors includes a first metal layer and a second metal layer having a work function higher than a work function of the first metal layer.

20. The semiconductor device of claim 19, wherein the first gate electrode layer of the n-type transistors includes the first metal layer.