Apparatuses and methods for access based refresh timing

• US 10,685,696 B2
• Filed: 10/31/2018
• Issued: 06/16/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Brown, Jason M., Penney, Daniel B.
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US16/176,932
• Publication Number:
  US 20200135263A1
• Time in Patent Office: 594 Days
• Field of Search: 365222
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/406 Refreshing of dynamic cells
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

Claims

1. An apparatus comprising:

a memory bank comprising word lines;

a row decoder configured to access a word line of the memory bank based on a received access address, and to refresh a word line of the memory bank based on a received refresh address;

an auto-refresh address generator configured to provide an auto-refresh address;

a targeted refresh address generator configured to provide a targeted refresh address; and

a cycle generator configured to determine if the auto-refresh address or the targeted refresh address is provided to the memory bank as the refresh address based on a count of the accesses to the memory bank.

2. The apparatus of claim 1, wherein the targeted refresh address generator is further configured to determine an aggressor address based on the received access addresses, determine a victim address based on the aggressor address, and provide the victim address as the targeted refresh address.

3. The apparatus of claim 1, further comprising a plurality of memory banks and a corresponding plurality of row decoders.

4. The apparatus of claim 3, wherein the cycle generator comprises a plurality of counters, each associated with one of the plurality of memory banks, wherein each of the counters is configured to count the received access addresses of the row decoder associated with the memory bank.

5. The apparatus of claim 3, further comprising a plurality of cycle generators, wherein each of the plurality of cycle generators is positioned in an associated one of the memory banks.

6. The apparatus of claim 1, wherein the the refresh address is provided responsive to a timing signal and wherein the cycle generator is configured to determine that a targeted refresh address is provided only during certain activations of the timing signal.

7. The apparatus of claim 1, wherein the auto-refresh addresses are periodically provided responsive to a timing signal, and wherein the targeted refresh address is provided instead of one of the auto-refresh address responsive to the count being equal to or greater than a threshold value.