Erase page check

• US 10,685,731 B2
• Filed: 05/13/2019
• Issued: 06/16/2020
• Est. Priority Date: 08/31/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Luo, Ting, Stoller, Scott Anthony, Thomson, Preston Allen, Batutis, Devin, Singidi, Harish Reddy, Tanpairoj, Kulachet
• Primary Examiner(s): Smet, Uyen
• Application Number:
  US16/410,764
• Publication Number:
  US 20200005884A1
• Time in Patent Office: 400 Days
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/50016 of retention

Abstract

Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.

Claims

1. A method performed by a memory device, the method comprising:

identifying a memory cell of the memory device to test for an incomplete programming, the memory cell configured to store multiple bits;

identifying a first read voltage used to read a first bit of the memory cell, the first read voltage having a lower read voltage than other read voltages used to read other bits stored in the memory cell;

testing for the incomplete programming by reducing the first read voltage by a specified amount and reading a value in the first bit of the memory cell using the reduced first read voltage;

determining that the memory cell was incompletely programmed based upon the value read from the memory cell;

in response to determining that the memory cell was incompletely programmed, mark the memory cell; and

wherein reading the value does not occur while in an administrative mode of the memory device.

2. The method of claim 1, wherein the first bit is a first page of the memory cell.

3. The method of claim 1, further comprising:

detecting an asynchronous power loss based upon determining that a shut-down indicator is not present and identifying the memory cell responsive to detecting the asynchronous power loss.

4. The method of claim 3, further comprising:

receiving an indication that a synchronous shut down is in process;

responsive to the indication that the synchronous shut down is in process, setting a shut-down indicator flag;

upon a subsequent power up, detecting that the shut-down indicator flag is set; and

responsive to detecting that the shut-down indicator flag is set, refraining from testing memory cells for incomplete programming.

5. The method of claim 1, wherein identifying the memory cell of the memory device comprises finding a last fully written memory cell.

6. The method of claim 1, wherein the memory cell is capable of storing one of:

two bits, three bits or four bits of data.

7. The method of claim 1, wherein the memory cell is marked for erasure.

8. The method of claim 1, wherein the method further comprises:

identifying a second memory cell of the memory device to test for the incomplete programming, the second memory cell configured to store multiple bits;

reading a second value in a first bit of the second memory cell using the reduced first read voltage;

determining that the second memory cell was not incompletely programmed based upon the value; and

in response to determining that the second memory cell was not incompletely programmed, mark the second memory cell as empty.

9. A memory device comprising:

a controller, configured to perform operations comprising;

identifying a memory cell of the memory device to test for an incomplete programming, the memory cell configured to store multiple bits;

identifying a first read voltage used to read a first bit of the memory cell, the first read voltage having a lower read voltage than other read voltages used to read other bits stored in the memory cell;

testing for the incomplete programming by reducing the first read voltage by a specified amount and reading a value in the first bit of the memory cell using the reduced first read voltage;

determining that the memory cell was incompletely programmed based upon the value read from the memory cell;

in response to determining that the memory cell was incompletely programmed, mark the memory cell; and

wherein reading the value does not occur while in an administrative mode of the memory device.

10. The memory device of claim 9, wherein the first bit is a first page of the memory cell.

11. The memory device of claim 9, wherein the operations further comprise:

detecting an asynchronous power loss based upon determining that a shut-down indicator is not present and identifying the memory cell responsive to detecting the asynchronous power loss.

12. The memory device of claim 11, wherein the operations further comprise:

receiving an indication that a synchronous shut down is in process;

responsive to the indication that the synchronous shut down is in process, setting a shut-down indicator flag;

upon a subsequent power up, detecting that the shut-down indicator flag is set; and

responsive to detecting that the shut-down indicator flag is set, refraining from testing memory cells for incomplete programming.

13. The memory device of claim 9, wherein the operations of identifying the memory cell of the memory device comprises finding a last fully written memory cell.

14. The memory device of claim 9, wherein the memory cell is capable of storing one of:

two bits, three bits or four bits of data.

15. The memory device of claim 9, wherein the memory cell is marked for erasure.

16. The memory device of claim 9, wherein the operations further comprise:

identifying a second memory cell of the memory device to test for the incomplete programming, the second memory cell configured to store multiple bits;

reading a second value in a first bit of the second memory cell using the reduced first read voltage;

determining that the second memory cell was not incompletely programmed based upon the value; and

in response to determining that the second memory cell was not incompletely programmed, mark the second memory cell as empty.

17. A machine-readable medium, storing instructions, which when executed by a machine, causes the machine to perform operations comprising:

identifying a memory cell of a memory device to test for an incomplete programming, the memory cell configured to store multiple bits;

identifying a first read voltage used to read a first bit of the memory cell, the first read voltage having a lower read voltage than other read voltages used to read other bits stored in the memory cell;

testing for the incomplete programming by reducing the first read voltage by a specified amount and reading a value in the first bit of the memory cell using the reduced first read voltage;

determining that the memory cell was incompletely programmed based upon the value read from the memory cell;

in response to determining that the memory cell was incompletely programmed, mark the memory cell; and

wherein reading the value does not occur while in an administrative mode of the memory device.

18. The machine-readable medium of claim 17, wherein the first bit is a first page of the memory cell.

19. The machine-readable medium of claim 17, wherein the operations further comprise:

detecting an asynchronous power loss based upon determining that a shut-down indicator is not present and identifying the memory cell responsive to detecting the asynchronous power loss.

20. The machine-readable medium of claim 17, wherein the operations further comprise:

receiving an indication that a synchronous shut down is in process;

responsive to the indication that the synchronous shut down is in process, setting a shut-down indicator flag;

upon a subsequent power up, detecting that the shut-down indicator flag is set; and

responsive to detecting that the shut-down indicator flag is set, refraining from testing memory cells for incomplete programming.