Semiconductor structures and fabrication methods thereof
First Claim
1. A method for fabricating a semiconductor structure, comprising:
- forming a semiconductor base structure including a substrate and a plurality of fin structures formed on the substrate, wherein the substrate includes a peripheral region and a core region, fin structures formed in the peripheral region are first fin structures, and fin structures formed in the core region are second fin structures;
forming a first dummy gate structure on each first fin structure and a second dummy gate structure on each second fin structure;
forming a dielectric layer on the semiconductor base structure, wherein a top surface of the dielectric layer is leveled with top surfaces of the first dummy gate structures and the second dummy gate structures;
removing each first dummy gate structure to form a first opening in the dielectric layer, wherein a portion of the first fin structure is exposed in the first opening;
forming a first gate oxide layer on the exposed portion of each first fin structure;
after forming the first gate oxide layer on the exposed portion of each first fin structure, removing each second dummy gate structure to form a second opening in the dielectric layer, wherein a portion of the second fin structure is exposed in the second opening;
forming a gate dielectric layer to cover each first gate oxide layer, sidewall surfaces of each first opening, and bottom and sidewall surfaces of each second opening; and
forming a metal layer to cover the gate dielectric layer and fill up the first openings and the second openings, wherein the first gate oxide layer, the gate dielectric layer, and the metal layer formed in each first opening form a first gate structure, and the gate dielectric layer and the metal layer formed in each second opening form a second gate structure, wherein each first dummy gate structure includes a first dummy gate oxide layer and a first dummy gate electrode layer formed on the first dummy gate oxide layer, and wherein removing each first dummy gate structure includes;
forming a patterned layer to cover the core region, wherein the patterned layer exposes a top surface of the first dummy gate electrode layer;
performing a dry etching process to remove the first dummy gate electrode layer and the first dummy gate oxide layer using the patterned layer as an etch mask until a portion of the first fin structure is exposed and the first opening is formed in the dielectric layer; and
removing the patterned layer.
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Abstract
A method for fabricating a semiconductor structure includes providing a substrate including a core region and a peripheral region, forming a plurality of first fin structures in the peripheral region and a plurality of second fin structures in the core region, forming a first dummy gate structure including a first dummy oxide layer and a first dummy gate electrode layer on each first fin structure, and forming a second dummy gate structure including a second dummy oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate structure and then forming a first gate oxide layer on the exposed portion of each first fin structure, and removing each second dummy gate structure. Finally, the method includes forming a first gate structure on each first fin structure and a second gate structure on each second fin structure.
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Citations
17 Claims
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1. A method for fabricating a semiconductor structure, comprising:
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forming a semiconductor base structure including a substrate and a plurality of fin structures formed on the substrate, wherein the substrate includes a peripheral region and a core region, fin structures formed in the peripheral region are first fin structures, and fin structures formed in the core region are second fin structures; forming a first dummy gate structure on each first fin structure and a second dummy gate structure on each second fin structure; forming a dielectric layer on the semiconductor base structure, wherein a top surface of the dielectric layer is leveled with top surfaces of the first dummy gate structures and the second dummy gate structures; removing each first dummy gate structure to form a first opening in the dielectric layer, wherein a portion of the first fin structure is exposed in the first opening; forming a first gate oxide layer on the exposed portion of each first fin structure; after forming the first gate oxide layer on the exposed portion of each first fin structure, removing each second dummy gate structure to form a second opening in the dielectric layer, wherein a portion of the second fin structure is exposed in the second opening; forming a gate dielectric layer to cover each first gate oxide layer, sidewall surfaces of each first opening, and bottom and sidewall surfaces of each second opening; and forming a metal layer to cover the gate dielectric layer and fill up the first openings and the second openings, wherein the first gate oxide layer, the gate dielectric layer, and the metal layer formed in each first opening form a first gate structure, and the gate dielectric layer and the metal layer formed in each second opening form a second gate structure, wherein each first dummy gate structure includes a first dummy gate oxide layer and a first dummy gate electrode layer formed on the first dummy gate oxide layer, and wherein removing each first dummy gate structure includes; forming a patterned layer to cover the core region, wherein the patterned layer exposes a top surface of the first dummy gate electrode layer; performing a dry etching process to remove the first dummy gate electrode layer and the first dummy gate oxide layer using the patterned layer as an etch mask until a portion of the first fin structure is exposed and the first opening is formed in the dielectric layer; and removing the patterned layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for fabricating a semiconductor structure, comprising:
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forming a semiconductor base structure including a substrate and a plurality of fin structures formed on the substrate, wherein the substrate includes a peripheral region and a core region, fin structures formed in the peripheral region are first fin structures, and fin structures formed in the core region are second fin structures; forming a first dummy gate structure on each first fin structure and a second dummy gate structure on each second fin structure; forming a dielectric layer on the semiconductor base structure, wherein a top surface of the dielectric layer is leveled with top surfaces of the first dummy gate structures and the second dummy gate structures; removing each first dummy gate structure to form a first opening in the dielectric layer, wherein a portion of the first fin structure is exposed in the first opening; forming a first gate oxide layer on the exposed portion of each first fin structure; after forming the first gate oxide layer on the exposed portion of each first fin structure, removing each second dummy gate structure to form a second opening in the dielectric layer, wherein a portion of the second fin structure is exposed in the second opening; forming a gate dielectric layer to cover each first gate oxide layer, sidewall surfaces of each first opening, and bottom and sidewall surfaces of each second opening; and forming a metal layer to cover the gate dielectric layer and fill up the first openings and the second openings, wherein the first gate oxide layer, the gate dielectric layer, and the metal layer formed in each first opening form a first gate structure, and the gate dielectric layer and the metal layer formed in each second opening form a second gate structure, wherein the second dummy gate structure includes a second dummy gate oxide layer and a second dummy gate electrode layer formed on the second dummy gate oxide layer, and wherein removing each second dummy gate structure includes; forming a patterned layer to cover the peripheral region, wherein the patterned layer exposes a top surface of the second dummy gate electrode layer; performing a dry etching process to remove the second dummy gate electrode layer and then the second dummy gate oxide layer using the patterned layer as an etch mask until a portion of the second fin structure is exposed and the second opening is formed in the dielectric layer; and removing the patterned layer.
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Specification