Integrated circuit device

• US 10,685,960 B2
• Filed: 10/23/2018
• Issued: 06/16/2020
• Est. Priority Date: 04/10/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Min-seong, Kim, Ju-youn, Yoon, Ji-hoon, Kim, Il-ryong, Yeo, Kyoung-hwan, Chung, Jae-yup
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US16/168,046
• Publication Number:
  US 20190312034A1
• Time in Patent Office: 602 Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

An integrated circuit device includes a first fin separation insulating portion over the first device region; a pair of first fin-type active regions apart from each other with the first fin separation insulating portion therebetween and collinearly extending in a first horizontal direction; a first dummy gate structure vertically overlapping the first fin separation insulating portion; a second fin separation insulating portion apart from the first fin separation insulating portion and arranged over the second device region; and a plurality of second fin-type active regions apart from each other with the second fin separation insulating portion therebetween in the second device region and collinearly extending in the first horizontal direction, wherein a vertical level of a lowermost surface of the second fin separation insulating portion is equal to or lower than a vertical level of a lowermost surface of the first fin separation insulating portion.

Claims

1. An integrated circuit device comprising:

a substrate comprising a first device region and a second device region;

a first fin separation insulating portion over the first device region;

a pair of first fin-type active regions spaced apart from each other in the first device region, with the first fin separation insulating portion therebetween, a first element of the pair of first fin-type active regions collinearly extending in a first horizontal direction with a second element of the pair of first fin-type active regions;

a first dummy gate structure covering an upper surface of the first fin separation insulating portion to vertically overlap the first fin separation insulating portion, and extending in a second horizontal direction over the first device region, the second horizontal direction crossing the first horizontal direction;

a second fin separation insulating portion spaced apart from the first fin separation insulating portion and arranged over the second device region, and collinearly extending with the first dummy gate structure in the second horizontal direction; and

a plurality of second fm-type active regions spaced apart from each other in the second device region with the second fin separation insulating portion therebetween, the plurality of second fin-type active regions collinearly extending in the first horizontal direction,

wherein a vertical level of a lowermost surface of the second fin separation insulating portion is lower than a vertical level of a lowermost surface of the first fin separation insulating portion.

2. The integrated circuit device of claim 1, wherein a vertical level of an uppermost surface of the first fin separation insulating portion is lower than a vertical level of an uppermost surface of the pair of first fin-type active regions.

3. The integrated circuit device of claim 1, wherein a vertical level of an uppermost surface of the second fin separation insulating portion is higher than a vertical level of an uppermost surface of the first fin separation insulating portion.

4. The integrated circuit device of claim 1, wherein a vertical level of an uppermost surface of the second fin separation insulating portion is higher than a vertical level of an uppermost surface of the first dummy gate structure.

5. The integrated circuit device of claim 1, wherein the vertical level of the lowermost surface of the second fin separation insulating portion is lower than a vertical level of a lowermost surface of each of the plurality of second fin-type active regions.

6. The integrated circuit device of claim 1, wherein

the first fin separation insulating portion has a first width in the first horizontal direction, and

the second fin separation insulating portion has a second width in the first horizontal direction, the second width being less than the first width.

7. The integrated circuit device of claim 1, wherein, in the first horizontal direction, a width of the second fin separation insulating portion is greater than a width of the first dummy gate structure.

8. The integrated circuit device of claim 1, wherein the first dummy gate structure comprises:

a first portion vertically overlapping the first fin separation insulating portion; and

a second portion vertically overlapping one first fin-type active region from among the pair of first fin-type active regions,

wherein a vertical length of the first portion is greater than a vertical length of the second portion.

9. The integrated circuit device of claim 1, further comprising:

a second dummy gate structure covering the upper surface of the first fin separation insulating portion to vertically overlap the first fin separation insulating portion, and extending in the second horizontal direction over the first device region; and

a third fin separation insulating portion spaced apart from the first fin separation insulating portion and arranged over the second device region, and collinearly extending with the second dummy gate structure in the second horizontal direction.

10. The integrated circuit device of claim 1, further comprising:

a pair of third dummy gate structures spaced apart from each other with the second fin separation insulating portion therebetween and collinearly extending in the second horizontal direction,

wherein one of the pair of third dummy gate structures vertically overlaps the first fin separation insulating portion over the first device region.

11. An integrated circuit device comprising:

a substrate comprising a first device region and a second device region;

a first fin separation insulating portion in the first device region;

a pair of first fin-type active regions spaced apart from each other in the first device region with the first fin separation insulating portion therebetween, one element of the pair of first fin-type active regions collinearly extending in a first horizontal direction with the other element of the pair of first fin-type active regions;

a plurality of dummy gate structures extending parallel to each other in a second horizontal direction over the first fin separation insulating portion, the second horizontal direction crossing the first horizontal direction;

at least one second fin separation insulating portion spaced apart from the first fin separation insulating portion and arranged over the second device region; and

a plurality of second fin-type active regions spaced apart from each other in the second device region with the at least one second fin separation insulating portion therebetween and collinearly extending in the first horizontal direction,

wherein a vertical level of a lowermost surface of the at least one second fin separation insulating portion is equal to or lower than a vertical level of a lowermost surface of the first fin separation insulating portion.

12. The integrated circuit device of claim 11, wherein the at least one second fin separation insulating portion collinearly extends with at least one dummy gate structure selected from the plurality of dummy gate structures.

13. The integrated circuit device of claim 11, wherein a vertical level of a lowermost surface of the plurality of dummy gate structures is lower than a vertical level of an uppermost surface of the pair of first fin-type active regions.

14. The integrated circuit device of claim 11, wherein the at least one second fin separation insulating portion comprises:

an upper insulating portion at the second device region, the upper insulating portion extending in the second horizontal direction; and

a plurality of lower insulating portions integrally connected to the upper insulating portion, the plurality of lower insulating portions protruding from the upper insulating portion toward the substrate.

15. The integrated circuit device of claim 11, further comprising:

a gate structure over the first device region and the second device region, the gate structure extending parallel to the plurality of dummy gate structures,

wherein a vertical level of an uppermost surface of the at least one second fin separation insulating portion is higher than a vertical level of an uppermost surface of the gate structure, and the vertical level of the lowermost surface of the at least one second fin separation insulating portion is lower than the vertical level of the lowermost surface of the first fin separation insulating portion.

16. The integrated circuit device of claim 11, wherein the first fin separation insulating portion has a first width in the first horizontal direction, and

a plurality of second fin separation regions are arranged on a region of the second device region, and a sum of widths of the plurality of second fin separation regions in the first direction is less than or equal to the first width.

17. An integrated circuit device comprising:

a substrate comprising a first device region and a second device region spaced apart from each other;

a device isolation region between the first device region and the second device region;

a first fin separation insulating portion over the first device region;

a plurality of pairs of first fm-type active regions in the first device region, each of the plurality of pairs of first fin-type active regions including a first member and a second member, each of the plurality of pairs of first fin-type active regions vertically protruding from the substrate at the first device region, and each of the plurality of pairs of first fin-type active regions having the first member spaced apart from second member with the first fin separation insulating portion therebetween, each of the plurality of pairs having the first member collinearly extending with the second member in a first horizontal direction;

a plurality of second fin separation insulating portions extending in a second horizontal direction over the second device region and spaced apart from each other, wherein the second horizontal direction crosses the first horizontal direction; and

a plurality of second fin-type active regions vertically protruding from the substrate at the second device region and arranged in a straight line extending in the first horizontal direction across the plurality of second fin separation insulating portions,

wherein a vertical level of a lowermost surface of the plurality of second fin separation insulating portions is lower than a vertical level of a lowermost surface of the first fin separation insulating portion.

18. The integrated circuit device of claim 17, further comprising:

a plurality of dummy gate structures over the first fin separation insulating portion extending parallel to each other in the second horizontal direction; and

a gate structure spaced apart from the first fin separation insulating portion in the first horizontal direction and extending parallel to the plurality of dummy gate structures over the first device region,

wherein a vertical level of an uppermost surface of the plurality of second fin separation insulating portions is higher than a vertical level of an uppermost surface of the gate structure, and the vertical level of the lowermost surface of the plurality of second fin separation insulating portions is lower than the vertical level of the lowermost surface of the first fin separation insulating portion.

19. The integrated circuit device of claim 18, wherein each of the plurality of second fin separation insulating portions contacts one dummy gate structure selected from the plurality of dummy gate structures.

20. The integrated circuit device of claim 18, wherein the first fin separation insulating portion vertically overlaps at least three dummy gate structures from among the plurality of dummy gate structures.