Semiconductor structure for preventing row hammering issue in DRAM cell and method for manufacturing the same

• US 10,685,964 B2
• Filed: 07/05/2018
• Issued: 06/16/2020
• Est. Priority Date: 05/18/2017
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Tsai, Chih-Chieh, Chen, Pin-Hong, Chen, Tzu-Chieh, Cheng, Tsun-Min, Chen, Yi-Wei, Huang, Hsin-Fu, Hsu, Chi-Mao, Tzou, Shih-Fang
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US16/028,364
• Publication Number:
  US 20180337187A1
• Time in Patent Office: 712 Days
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

Claims

1. A semiconductor structure for preventing row hammering issue in DRAM cell, comprising:

a substrate;

a plurality of trenches comprising a first trench and a second trench, wherein said first trench is deeper than said second trench;

a shallow trench isolation comprising an upper portion and a lower portion disposed in said first trench, wherein said upper portion is disposed on said lower portion and has a different material composition from said lower portion, and said lower portion directly contacts and covers around entire perimeter surface of said first trench, and said upper portion has a top surface being higher than a bottom surface of said second trench, and a thickness of said lower portion is thicker at bottom than at sidewalls thereof, and said top surface of said upper portion of said shallow trench isolation has a convexly-curved shape;

a gate dielectric conformally on said second trench and conformally on said lower portion and said upper portion of said shallow trench isolation in said first trench;

an n-type work function metal layer conformally on and directly contacting said gate dielectric;

a titanium nitride layer conformally on said n-type work function metal layer; and

a buried word line on said titanium nitride layer in said trenches, wherein an entire top surface of said buried word line is flat.

2. The semiconductor structure for preventing row hammering issue in DRAM cell of claim 1, further comprising a hard mask on said buried word line.

3. The semiconductor structure for preventing row hammering issue in DRAM cell of claim 2, wherein a material of said hard mask is silicon nitride.

4. The semiconductor structure for preventing row hammering issue in DRAM cell of claim 1, wherein a material of said n-type work function metal layer is chosen from Ti, TiAl, ZrAl, WAl, TaAl, HfAl, TiAlC, or any combination thereof.

5. The semiconductor structure for preventing row hammering issue in DRAM cell of claim 1, wherein a material of said gate dielectric is chosen from HfO₂, HfSiO₄, HfSiON, Al₂O₃, La₂O₃, Ta₂O₅, Y₂O₃, ZrO₂, SrTiO₃, ZrSiO₄, HfZrO₄, SrBi₂Ta₂O₉ (SBT), PbZr_xTi_1-xO₃ (PZT), Ba_xSr_1-xTiO₃ (BST), or any combination thereof.

6. The semiconductor structure for preventing row hammering issue in DRAM cell of claim 1, wherein a material of said buried word line is chosen from Cu, Al, W, TiAl, CoWP, or any combination thereof.