Fin damage reduction during punch through implantation of FinFET device

• US 10,686,033 B2
• Filed: 11/09/2018
• Issued: 06/16/2020
• Est. Priority Date: 11/09/2018
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Sung, Min Gyu, Lee, Jae Young, Van Meer, Johannes, Varghese, Sony, Variam, Naushad K.
• Primary Examiner(s): Maruf, Sheikh
• Application Number:
  US16/186,027
• Publication Number:
  US 20200152735A1
• Time in Patent Office: 585 Days
• Field of Search: 438371
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, and forming a second STI material over a second fin section of the plurality of fins, wherein the second fin section is left remaining following removal of the first fin section. The method may further include recessing the STI material and the second STI material, forming a spin-on-carbon (SOC) layer over the semiconductor device, and implanting the STI material and the second STI material through the SOC layer.

Claims

1. A method, comprising:

providing a semiconductor device including a substrate and a plurality of fins extending from the substrate;

forming a source trench isolation (STI) material over the semiconductor device;

performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, wherein the first fin section and the first portion of the STI material are removed to a top surface of the substrate;

forming a second STI material over a second fin section of the plurality of fins, the second fin section remaining following removal of the first fin section;

recessing the STI material and the second STI material;

forming a spin-on-carbon (SOC) layer over the semiconductor device; and

implanting the STI material and the second STI material, through the SOC layer.

2. The method of claim 1, further comprising removing the SOC layer after the implanting.

3. The method of claim 1, further comprising forming a resist layer atop the SOC layer.

4. The method of claim 1, further comprising providing a hardmask layer atop the plurality of fins.

5. The method of claim 4, further comprising removing the hardmask layer after the implanting.

6. The method of claim 1, further comprising:

forming a dielectric layer over the plurality of fins; and

forming the STI material over the dielectric layer.

7. The method of claim 1, further comprising recessing the STI material and the second STI material to reveal the second fin section of the plurality of fins.

8. The method of claim 1, wherein the second fin section of the plurality of fins includes a first fin and a second fin, and wherein a second portion of the STI material remains between the first fin and the second fin following the fin cut.

9. A method of forming a semiconductor device, comprising:

providing the semiconductor device including a substrate and a plurality of fins extending from the substrate;

forming a source trench isolation (STI) material between the plurality of fins;

performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, wherein the first fin section and the first portion of the STI material are removed to a top surface of the substrate;

forming a second STI material over a second fin section of the plurality of fins, the second fin section remaining following removal of the first fin section;

recessing the STI material and the second STI material;

forming a spin-on-carbon (SOC) layer over the STI material, the second STI material, and the second fin section; and

implanting the STI material and the second STI material, through the SOC layer.

10. The method of claim 9, further comprising forming a resist layer atop the SOC layer.

11. The method of claim 9, further comprising providing a hardmask layer atop the plurality of fins.

12. The method of claim 11, further comprising removing the hardmask layer and the SOC layer after the implanting.

13. The method of claim 9, further comprising:

forming a dielectric layer over the plurality of fins; and

forming the STI material over the dielectric layer.

14. The method of claim 9, further comprising recessing the STI material and the second STI material to reveal an upper portion of the second fin section of the plurality of fins.

15. The method of claim 9, wherein the second fin section of the plurality of fins includes a first fin and a second fin, and wherein a second portion of the STI material remains between the first fin and the second fin following the fin cut.

16. A method of forming a finFET device, comprising:

providing a plurality of fins extending from a substrate;

forming a source trench isolation (STI) material between the plurality of fins;

performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, wherein the first fin section and the first portion of the STI material are removed to a top surface of the substrate;

forming a second STI material over a second fin section of the plurality of fins, the second fin section remaining following removal of the first fin section;

recessing the STI material and the second STI material;

forming a spin-on-carbon (SOC) layer over the STI material, the second STI material, and the second fin section; and

implanting the STI material and the second STI material, through the SOC layer.

17. The method of claim 16, further comprising forming a resist layer atop the SOC layer.

18. The method of claim 16, further comprising providing a hardmask layer atop the plurality of fins, wherein the hardmask layer and the SOC layer are removed after the implanting.

19. The method of claim 16, further comprising:

forming a dielectric layer over the plurality of fins; and

forming the STI material over the dielectric layer.

20. The method of claim 16, further comprising recessing the STI material and the second STI material to reveal an upper portion of the second fin section of the plurality of fins.