Method for manufacturing trench MOSFET

• US 10,686,058 B2
• Filed: 10/02/2018
• Issued: 06/16/2020
• Est. Priority Date: 10/11/2017
• Status: Active Grant

• Current Assignee: Hangzhou Silicon-Magic Semiconductor Technology Company Limited
• Original Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Inventors: Cai, Jinyong, Liao, Zhongping
• Primary Examiner(s): Ho, Anthony
• Assistant Examiner(s): Quinto, Kevin
• Application Number:
  US16/149,255
• Publication Number:
  US 20190109216A1
• Time in Patent Office: 623 Days
• Field of Search: None
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of manufacturing a trench MOSFET can include: forming an epitaxial semiconductor layer having a first doping type on a semiconductor substrate; forming a trench extending from a first surface of the epitaxial semiconductor layer to an internal portion of the epitaxial semiconductor layer; forming a first insulating layer and a shield conductor occupying a lower portion of said trench, where the first insulating layer is located on a lower sidewall surface and a bottom surface of the trench and separates the shield conductor from the epitaxial semiconductor layer; forming a second insulating layer covering a top surface of said shield conductor, where the second insulating layer is patterned by using a hard mask; forming a gate dielectric layer and a gate conductor occupying an upper portion of the trench; and forming a body region, a source region, and a drain electrode.

Claims

1. A method of manufacturing a trench metal-oxide-semiconductor field-effect transistor (MOSFET), the method comprising:

a) forming an epitaxial semiconductor layer having a first doping type on a semiconductor substrate;

b) forming a trench extending from a first surface of said epitaxial semiconductor layer to an internal portion of said epitaxial semiconductor layer;

c) forming a first insulating layer and a shield conductor occupying a lower portion of said trench, wherein said first insulating layer is located on a lower sidewall surface and a bottom surface of said trench and separates said shield conductor from said epitaxial semiconductor layer;

d) forming a second insulating layer covering a top surface of said shield conductor and conformally occupying an upper portion of said trench and covering an upper sidewall surface of said trench, wherein said forming said second insulating layer comprises filling up the upper portion of said trench with a hard mask layer, etching back a portion of said hard mask layer, etching and removing a portion of said second insulating layer on the upper sidewall surface of said trench using said hard mask layer, and removing said hard mask layer;

e) forming a gate dielectric layer and a gate conductor occupying the upper portion of said trench, wherein said gate dielectric layer is located on the upper sidewall surface of said trench and separates said gate conductor from said epitaxial semiconductor layer; and

f) forming a body region, a source region, and a drain electrode.

2. The method of claim 1, wherein said first insulating layer comprises an oxide layer formed by a thermal oxidation or a low pressure chemical vapor deposition process.

3. The method of claim 1, wherein said second insulating layer comprises an oxide layer formed by a low pressure chemical vapor deposition or a plasma enhanced chemical vapor deposition process.

4. The method of claim 1, wherein said gate dielectric layer comprises an oxide layer formed by thermal oxidation process.

5. The method of claim 1, wherein said hard mask layer filling the upper portion of said trench comprises nitrides.

6. The method of claim 1, wherein said hard mask layer comprises a polysilicon layer.

7. The method of claim 6, wherein said filling up the upper portion of said trench with said polysilicon layer comprises:

a) depositing said polysilicon layer having a first portion in said trench and a second portion on said first surface of said epitaxial semiconductor layer; and

b) removing said second portion of said polysilicon layer to expose a top portion of said second insulating layer.

8. The method of claim 7, further comprising removing at least a portion of said first portion of said polysilicon layer by an etching back process.

9. The method of claim 7, wherein said etching back process comprises a dry etching process.

10. The method of claim 6, wherein each of said shield conductor and said gate conductor comprises said polysilicon layer formed by a low pressure chemical vapor deposition process.

11. The method of claim 1, further comprising:

a) forming said body region having a second doping type in an upper region of said epitaxial semiconductor layer adjacent to the trench, wherein said second doping type is opposite to said first doping type;

b) forming said source region having said first doping type in said body region; and

c) forming said drain electrode on a second surface of said semiconductor substrate, wherein said second surface and said first surface of said semiconductor substrate are opposite to each other.

12. The method of claim 11, wherein said first doping type is one of N type and P type, and said second doping type is the other one of N type and P type.

13. The method of claim 11, further comprising after the formation of said source region:

a) forming an interlayer dielectric layer on said source region and said gate conductor; and

b) forming a source electrode on said interlayer dielectric layer.

14. The method of claim 13, further comprising:

a) forming a body contact region having said second doping type in said body region; and

b) forming a conductive channel penetrating said interlayer dielectric layer and said source region to said body contact region, wherein said source electrode is connected to said body contact region via said conductive channel.

15. A trench metal-oxide-semiconductor field-effect transistor (MOSFET) formed by the method of claim 1, the MOSFET comprising:

a) a trench extending from a first surface of an epitaxial semiconductor layer to an internal portion of said epitaxial semiconductor layer;

b) a first insulating layer and a shield conductor that cover a lower portion of said trench;

c) a second insulating layer that covers a top surface of said shield conductor; and

d) a gate dielectric layer and a gate conductor that cover the upper portion of said trench.

16. The MOSFET of claim 15, wherein a thickness of said second insulating layer is uniform.

17. The MOSFET of claim 15, wherein a quality of said second insulating layer is uniform.