Apparatus and method for power MOS transistor

• US 10,686,065 B2
• Filed: 12/06/2018
• Issued: 06/16/2020
• Est. Priority Date: 07/11/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Chou, Hsueh-Liang, Su, Po-Chih, Liu, Ruey-Hsin
• Primary Examiner(s): Tran, Dzung
• Application Number:
  US16/211,422
• Publication Number:
  US 20190109229A1
• Time in Patent Office: 558 Days
• Field of Search: 257330
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/10 with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.

Claims

1. A method comprising:

forming a first semiconductor layer over a substrate;

forming a second semiconductor layer over the first semiconductor layer;

forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench;

forming a dielectric region in the first trench; and

forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.

2. The method of claim 1, wherein:

a depth of the first trench is substantially equal to a depth of the second trench;

the first semiconductor layer is a buried layer; and

the second semiconductor layer is an epitaxial layer.

3. The method of claim 1, wherein:

a width of the second trench is greater than a width of the first trench.

4. The method of claim 1, further comprising:

depositing a dielectric material in the first trench and the second trench, wherein the dielectric material fully fills the first trench and partially fills the second trench.

5. The method of claim 4, wherein:

a middle portion of the second trench is free of the dielectric material.

6. The method of claim 4, further comprising:

applying an etching process to the dielectric material in the first trench and the second trench.

7. The method of claim 6, wherein:

as a result of applying the etching process to the dielectric material, the dielectric material in the first trench is partially removed and the dielectric material in the second trench is completely removed.

8. The method of claim 7, wherein:

a remaining portion of the dielectric material in the first trench forms the dielectric region.

9. The method of claim 7, wherein:

a thickness of the dielectric region is in a range from about 0.5 um to about 5 um.

10. The method of claim 7, further comprising:

after the step of applying the etching process to the dielectric material in the first trench and the second trench, depositing a gate dielectric layer in the first trench and the second trench;

forming a first gate electrode region and a second gate electrode region in the first trench and the second trench respectively; and

forming a source region and a drain region, wherein the drain region and the source region are on opposite sides of the first trench.

11. A method comprising:

forming a plurality of semiconductor layers over a substrate;

forming a first trench and a second trench through in the plurality of semiconductor layers, wherein a width of the second trench is greater than a width of the first trench;

partially filling the first trench with a dielectric material; and

forming a first gate region and a second gate region in the first trench and the second trench, respectively.

12. The method of claim 11, further comprising:

after forming the first trench and the second trench, forming a dielectric layer in the first trench and the second trench, wherein the dielectric layer completely fills the first trench and partially fills the second trench.

13. The method of claim 12, further comprising:

completely removing the dielectric layer in the second trench; and

partially removing the dielectric layer in the first trench.

14. The method of claim 11, further comprising:

depositing a gate dielectric layer in the first trench and the second trench;

forming a first gate electrode region and a second gate electrode region in the first trench and the second trench respectively; and

forming a source region and a drain region, wherein the drain region and the source region are on opposite sides of the first trench.

15. The method of claim 11, wherein:

a bottom of the first trench is substantially level with a bottom of the second trench.

16. A method comprising:

forming a plurality of semiconductor layers over a substrate;

applying an etching process to the plurality of semiconductor layers to form a first trench and a second trench, wherein a depth of the second trench is approximately equal to a depth of the first trench;

partially filling the first trench with a dielectric material; and

forming a first gate region and a second gate region in the first trench and the second trench respectively.

17. The method of claim 16, further comprising:

forming a first drain/source region and a second drain/source region in the plurality of semiconductor layers, wherein the first drain/source region and the second drain/source region are on opposite sides of the first trench.

18. The method of claim 16, wherein:

the plurality of semiconductor layers comprises a buried layer over the substrate and an epitaxial layer over the buried layer.

19. The method of claim 16, wherein:

a width of the first trench is greater than a width of the second trench.

20. The method of claim 16, further comprising:

depositing a dielectric material in the first trench and the second trench, wherein the dielectric material fully fills the first trench and partially fills the second trench; and

applying an etching process to the dielectric material in the first trench and the second trench, wherein as a result of applying the etching process to the dielectric material, the dielectric material in the first trench is partially removed and the dielectric material in the second trench is completely removed.