High-sensitivity clocked comparator and method thereof

• US 10,686,431 B1
• Filed: 10/18/2019
• Issued: 06/16/2020
• Est. Priority Date: 10/18/2019
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Lin, Chia-Liang (Leon)
• Primary Examiner(s): O Neill, Patrick
• Application Number:
  US16/656,801
• Time in Patent Office: 242 Days
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/45264 Complementary cross coupled types
• CPC Class Codes: H03K 3/0233 Bistable circuits
• CPC Class Codes: H03K 3/02335 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/356191 with synchronous operation
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03K 5/249 using clock signals

Abstract

A clocked comparator includes a first clocked transconductance amplifier configured to receive a first voltage signal and output a first current signal to an internal node in accordance with a clock; a clocked regenerative load configured to enable a second voltage signal at the internal node to self-regenerate in accordance with the clock; a SR (set-reset) latch configured to receive the second voltage signal at the internal node and output a third voltage signal; and a second clocked transconductance amplifier configured to receive the third voltage signal and output a second current signal to the internal node.

Claims

1. A clocked comparator comprising:

a first clocked transconductance amplifier configured to receive a first voltage signal and output a first current signal to an internal node in accordance with a clock;

a clocked regenerative load configured to enable a second voltage signal at the internal node to self-regenerate in accordance with the clock;

a SR (set-reset) latch configured to receive the second voltage signal at the internal node and output a third voltage signal; and

a second clocked transconductance amplifier configured to receive the third voltage signal and output a second current signal to the internal node.

2. The clocked comparator of claim 1, wherein the third voltage signal conforms to the same state of the second voltage signal when the second voltage is in a resolved state, and otherwise remains in a previous state.

3. The clocked comparator of claim 2, wherein the first clocked transconductance amplifier comprises a first clocked common-source amplifier configured to receive the first voltage signal and output a fourth voltage signal in accordance with the clock, and a first common-gate amplifier configured to receive the fourth voltage signal and output the first current signal.

4. The clocked comparator of claim 3, wherein the first common-gate amplifier is of a cross-coupling topology.

5. The clocked comparator of claim 4, wherein:

the second clocked transconductance amplifier comprises a second clocked common-source amplifier configured to receive the third voltage signal and output a fifth voltage signal in accordance with the clock, and a second common-gate amplifier configured to receive the fifth voltage signal and output the second current signal.

6. The clocked comparator of claim 5, wherein the second common-gate amplifier is of a cross-coupling topology.

7. The clocked comparator of claim 6, wherein when the clock is in a first logical state, the first clocked common-source amplifier and the second clocked common-source amplifier are turned off, consequently turning off the first common-gate amplifier and the second common-gate amplifier and zeroing the first current signal and the second current signal, the clocked regenerative load is turned off, and the second voltage signal is reset to a null state.

8. The clocked comparator of claim 7, wherein upon a transition of the clock from the first logical state to a second logical state, the first clocked common-source amplifier and the second clocked common-source amplifier are turned on to develop the fourth voltage signal and the fifth voltage signal in accordance with the first voltage signal and the third voltage signal and consequently develop the first current signal and the second current signal via the first common-gate amplifier and the second common-gate amplifier, respectively, and the second voltage signal develops in accordance with the first current signal and the second current signal and self-regenerates into a resolved state.

9. The clocked comparator of claim 2, wherein the SR latch and the second clocked transconductance amplifier forms a negative feedback to help toggling a state of the third voltage signal upon the transition of the clock from a first logical state to a second logical state.

10. The clocked comparator of claim 9, wherein the first current signal and the second current signal are summed at the internal node with opposite polarity.

11. A method comprising:

converting a first voltage signal into a first current signal directed to an internal node using a first clocked transconductance amplifier controlled by a clock;

enabling a second voltage signal at the internal node to self-regenerate and develop into a resolved state using a clocked regenerative load controlled by the clock;

imposing the resolved state of the second voltage signal onto a third voltage signal using a SR (set-reset) latch; and

converting the third voltage signal into a second current signal directed to the internal node using a second clocked transconductance amplifier controlled by the clock.

12. The method of claim 11, wherein the third voltage signal conforms to the same state of the second voltage signal when the second voltage is in a resolved state, and otherwise remains in a previous state.

13. The method of claim 12, wherein the first clocked transconductance amplifier comprises a first clocked common-source amplifier configured to receive the first voltage signal and output a fourth voltage signal in accordance with the clock, and a first common-gate amplifier configured to receive the fourth voltage signal and output the first current signal.

14. The method of claim 13, wherein the first common-gate amplifier is of a cross-coupling topology.

15. The method of claim 14, wherein:

the second clocked transconductance amplifier comprises a second clocked common-source amplifier configured to receive the third voltage signal and output a fifth voltage signal in accordance with the clock, and a second common-gate amplifier configured to receive the fifth voltage signal and output the second current signal.

16. The method of claim 15, wherein the second common-gate amplifier is of a cross-coupling topology.

17. The method of claim 16, wherein when the clock is in a first logical state, the first clocked common-source amplifier and the second clocked common-source amplifier are turned off, consequently turning off the first common-gate amplifier and the second common-gate amplifier and zeroing the first current signal and the second current signal, the clocked regenerative load is turned off, and the second voltage signal is reset to a null state.

18. The method of claim 17, wherein upon a transition of the clock from the first logical state to a second logical state, the first clocked common-source amplifier and the second clocked common-source amplifier are turned on to develop the fourth voltage signal and the fifth voltage signal in accordance with the first voltage signal and the third voltage signal and consequently develop the first current signal and the second current signal via the first common-gate amplifier and the second common-gate amplifier, respectively, and the second voltage signal develops in accordance with the first current signal and the second current signal and self-regenerates into a resolved state.

19. The method of claim 12, wherein the SR latch and the second clocked transconductance amplifier forms a negative feedback to help toggling a state of the third voltage signal upon the transition of the clock from a first logical state to a second logical state.

20. The method of claim 19, wherein the first current signal and the second current signal are summed at the internal node with opposite polarity.