Discrete input determining circuit and method

• US 10,690,702 B2
• Filed: 07/26/2019
• Issued: 06/23/2020
• Est. Priority Date: 10/06/2017
• Status: Active Grant

• Current Assignee: GE Aviation Systems LLC (GE Aerospace)
• Original Assignee: GE Aviation Systems LLC (GE Aerospace)
• Inventors: Smythe, Douglas Clayton
• Primary Examiner(s): Cox, Cassandra F
• Application Number:
  US16/522,839
• Publication Number:
  US 20190346488A1
• Time in Patent Office: 333 Days
• Field of Search: None
• CPC Class Codes: G01R 15/04 Voltage dividers
• CPC Class Codes: G01R 19/0038 Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing pulses or pulse trains according to amplitude)
• CPC Class Codes: G01R 19/16557 Logic probes, i.e. circuits indicating logic state (high, low, O); modifications of electronic switches or gates for indicating state of switch H03K17/18
• CPC Class Codes: G01R 19/1659 to indicate that the value is within or outside a predetermined range of values (window) G01R19/16514, G01R19/16519, G01R19/16528 and G01R19/16533 take precedence
• CPC Class Codes: G01R 31/008 on air- or spacecraft, railway rolling stock or sea-going vessels
• CPC Class Codes: H02H 3/32 involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors

Abstract

A discrete input determining circuit is disclosed, which includes an input biasing network connected to a discrete input for providing a first input voltage, a voltage divider network for dividing the first input voltage into a second input voltage and a third input voltage, a first comparator, wherein a non-inverting input terminal of the first comparator receives the second input voltage, and a second comparator, wherein an inverting input terminal of the second comparator receives the third input voltage, wherein an inverting input terminal of the first comparator and a non-inverting input terminal of the second comparator receive a reference voltage, and an output terminal of the first comparator and an output terminal of the second comparator are configured to provide a logic output. A discrete input determining method is also disclosed.

Claims

1. A discrete input determining circuit, comprising:

an input biasing network connected to a discrete input for providing a first input voltage;

a voltage divider network for dividing the first input voltage into a second input voltage and a third input voltage;

a first comparator, wherein a non-inverting input terminal of the first comparator receives the second input voltage; and

a second comparator, wherein an inverting input terminal of the second comparator receives the third input voltage;

wherein an inverting input terminal of the first comparator and a non-inverting input terminal of the second comparator receive a reference voltage, and an output terminal of the first comparator and an output terminal of the second comparator are configured to provide a logic output; and

wherein the voltage divider network comprises a second resistive load between the second input voltage and the third input voltage and a third resistive load between the third input voltage and a ground.

2. The discrete input determining circuit according to claim 1, wherein the input biasing network comprises a first power supply and a first resistive load connected between the discrete input and the first power supply, and a node between the discrete input and the first resistive load is connected to the voltage divider network.

3. The discrete input determining circuit according to claim 1, wherein the first input voltage is less than a positive voltage of the discrete input.

4. The discrete input determining circuit according to claim 1, wherein the voltage divider network further comprises a fourth resistive load between the first input voltage and the second input voltage.

5. The discrete input determining circuit according to claim 1, wherein the output terminal of the first comparator and the output terminal of the second comparator are wired together to implement a logic AND function so as to provide the logic output.

6. The discrete input determining circuit according to claim 5, further comprising an output configuration network comprising a second power supply and a fifth resistive load connected between the second power supply and the logic output.

7. A method of determining a discrete input, comprising:

biasing the discrete input to provide a first input voltage;

dividing the first input voltage into a second input voltage and a third input voltage by way of a disposing a second resistive load between the second input voltage and the third input voltage and a third resistive load between the third input voltage and a ground;

comparing the second input voltage with a reference voltage and outputting a first output;

comparing the reference voltage with the third input voltage and outputting a second output; and

outputting a logic output by a logic function between the first output and the second output.

8. The method according to claim 7, wherein when the discrete input is in an OPEN state, the second input voltage is larger than the reference voltage so that the first output is a logic high level, and the reference voltage is larger than the third input voltage so that the second output is the logic high level.

9. The method according to claim 7, wherein when the discrete input is in a positive voltage state, the second input voltage is larger than the reference voltage so that the first output is a logic high level, and the reference voltage is less than the third input voltage so that the second output is a logic low level.

10. The method according to claim 7, wherein when the discrete input is in a GND state, the second input voltage is less than the reference voltage so that the first output is a logic low level, and the reference voltage is larger than the third input voltage so that the second output is a logic high level.

11. The method according to claim 7, wherein the logic function comprises a logic AND function, wherein the logic output is a logic high level when the discrete input is in an OPEN state, the logic output is a logic low level when the discrete input is in a GND state, and the logic output is a logic low level when the discrete input is in a positive voltage state.

12. A method of determining a discrete input, comprising:

biasing the discrete input to provide a first input voltage;

dividing the first input voltage into a second input voltage and a third input voltage;

comparing the second input voltage with a reference voltage and outputting a first output;

comparing the reference voltage with the third input voltage and outputting a second output; and

outputting a logic output by a logic function between the first output and the second output;

wherein the first input voltage is less than a positive voltage of the discrete input, and the second input voltage is less than the first input voltage, and the third input voltage is less than the second input voltage;

wherein the discrete input is any one of an OPEN state, positive voltage, and GND state;

wherein when the discrete input is in an OPEN state, the second input voltage is larger than the reference voltage so that the first output is a logic high level, and the reference voltage is larger than the third input voltage so that the second output is the logic high level;

wherein when the discrete input is in a positive voltage state, the second input voltage is larger than the reference voltage so that the first output is a logic high level, and the reference voltage is less than the third input voltage so that the second output is a logic low level;

wherein when the discrete input is in a GND state, the second input voltage is less than the reference voltage so that the first output is a logic low level, and the reference voltage is larger than the third input voltage so that the second output is a logic high level.

13. The method according to claim 12, wherein the logic function comprises a logic AND function, wherein the logic output is a logic high level when the discrete input is in an OPEN state, the logic output is a logic low level when the discrete input is in a GND state, and the logic output is a logic low level when the discrete input is in a positive voltage state.