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Separate memory controllers to access data in memory

  • US 10,691,344 B2
  • Filed: 05/30/2013
  • Issued: 06/23/2020
  • Est. Priority Date: 05/30/2013
  • Status: Active Grant
First Claim
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1. A system comprising:

  • a memory;

    a first memory controller coupled to the memory;

    a second memory controller separate from the first memory controller, the second memory controller to send at least one access command to the first memory controller, the at least one access command to read or write data of the memory and being timing non-deterministic with respect to a timing specification of the memory,wherein the first memory controller is responsive to the at least one access command to issue at least one command signal to the memory, the at least one command signal satisfying the timing specification of the memory,wherein the first memory controller is to notify the second memory controller regarding a latency associated with accessing the memory,wherein the second memory controller is to issue a refresh command to the first memory controller in response to the second memory controller detecting an idle period of the second memory controller,wherein the memory comprises one or more memory types and the first memory controller comprises one or more separate memory controllers, each memory of the one or more memory types corresponds to each separate memory controller of the first memory controller, respectively; and

    wherein the timing specification of the memory relates to a timing parameter associated with a power constraint and a timing parameter associated with a thermal constraint of each memory of the one or more memory types.

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