Neural network computing

• US 10,691,410 B2
• Filed: 07/18/2018
• Issued: 06/23/2020
• Est. Priority Date: 07/19/2017
• Status: Active Grant

• Current Assignee: Alibaba Group Holding Ltd.
• Original Assignee: Alibaba Group Holding Ltd.
• Inventors: Leng, Cong, Li, Hao, Dou, Zesheng, Zhu, Shenghuo, Jin, Rong
• Primary Examiner(s): Mai, Tan V
• Application Number:
  US16/039,221
• Publication Number:
  US 20190026076A1
• Time in Patent Office: 706 Days
• Field of Search: 708209
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 2207/4824 Neural networks
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00
• CPC Class Codes: G06F 5/08 having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register G06F5/065 takes precedence; shift registers per se G11C19/00
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 7/556 Logarithmic or exponential functions
• CPC Class Codes: G06N 3/02 Neural networks
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/08 Learning methods

Abstract

A method including receiving, by a processor, a computing instruction for a neural network, wherein the computing instruction for the neural network includes a computing rule for the neural network and a connection weight of the neural network, and the connection weight is a power of 2; and inputting, for a multiplication operation in the computing rule for the neural network, a source operand corresponding to the multiplication operation to a shift register, and performing a shift operation based on a connection weight corresponding to the multiplication operation, wherein the shift register outputs a target result operand as a result of the multiplication operation. The neural network uses a shift operation, and a neural network computing speed is increased.

Claims

1. A method comprising:

receiving a computing instruction for a neural network, the computing instruction for the neural network including a computing rule for the neural network and a connection weight of the neural network;

inputting, for a multiplication operation in the computing rule for the neural network, a source operand corresponding to the multiplication operation to a shift register;

performing a shift operation based on a connection weight corresponding to the multiplication operation.

2. The method of claim 1, further comprising outputting a target result operand as a result of the multiplication operation.

3. The method of claim 1, wherein the connection weight corresponding to the multiplication operation is 2 to the power of N, and N is an integer greater than zero.

4. The method of claim 3, wherein the inputting the source operand corresponding to the multiplication operation to the shift register includes:

inputting the source operand corresponding to the multiplication operation to the shift register; and

shifting to left N times.

5. The method of claim 1, wherein the connection weight corresponding to the multiplication operation is 2 to the power of negative N, and N is an integer greater than zero.

6. The method of claim 5, wherein the inputting the source operand corresponding to the multiplication operation to the shift register includes:

inputting the source operand corresponding to the multiplication operation to the shift register; and

shifting to right N times.

7. The method of claim 1, wherein the receiving the computing instruction for the neural network includes:

receiving, by a processor, the computing instruction for the neural network.

8. The method of claim 7, wherein the processor includes any one of the following processors:

a processor based on an x86 architecture;

a processor based on an Advanced Reduced instruction set computing Machine (ARM) architecture;

a processor based on a Microprocessor without Interlocked Piped Stages (MIPS) architecture; and

a processor based on a dedicated architecture.

9. The method of claim 7, wherein the processor does not include a multiplication operation unit.

10. The method of claim 1, wherein a number of bits of the source operand is not greater than a number of bits of a value that is capable to be stored in the shift register.

11. A processor comprising:

a value obtaining unit that receives a computing instruction for a neural network, the computing instruction for the neural network including a computing rule for the neural network and a connection weight of the neural network; and

a shift register that receives, for a multiplication operation in the computing rule for the neural network, a source operand corresponding to the multiplication operation;

performs a shift operation based on a connection weight corresponding to the multiplication operation; and

outputs a target result operand as a result of the multiplication operation.

12. The processor of claim 11, wherein:

the connection weight corresponding to the multiplication operation is 2 to the power of N, and N is an integer greater than zero; and

the shift register shifts the source operand to left N times.

13. The processor of claim 11, wherein:

the connection weight corresponding to the multiplication operation is 2 to the power of negative N, and N is an integer greater than zero; and

the shift register shifts the source operand to right N times.

14. The processor of claim 11, wherein the processor includes any one of the following processors:

a processor based on an x86 architecture;

a processor based on an Advanced Reduced instruction set computing Machine (ARM) architecture;

a processor based on a Microprocessor without Interlocked Piped Stages (MIPS) architecture; and

a processor based on a dedicated architecture.

15. The processor of claim 11, wherein a number of bits of the source operand is not greater than a number of bits of a value that is capable to be stored in the shift register.

16. The processor of claim 11, wherein the processor does not include a multiplication operation unit.

17. A method comprising:

receiving a computing instruction for a neural network, the computing instruction for the neural network including a computing rule for the neural network and a connection weight of the neural network, and the connection weight being a power of 2; and

performing, for a multiplication operation in the computing rule for the neural network, a shift operation on a source operand corresponding to the multiplication operation based on a connection weight corresponding to the multiplication operation.

18. The method of claim 17, further comprising:

using a result operand of the shift operation as a result of the multiplication operation.

19. The method of claim 17, wherein:

the connection weight corresponding to the multiplication operation is 2 to the power of N, and N is an integer greater than zero; and

the performing the shift operation on a source operand corresponding to the multiplication operation based on the connection weight corresponding to the multiplication operation includes;

shifting the source operand to left N times.

20. The method of claim 17, wherein:

the connection weight corresponding to the multiplication operation is 2 to the power of negative N, and N is an integer greater than zero; and

the performing the shift operation on a source operand corresponding to the multiplication operation based on the connection weight corresponding to the multiplication operation includes;

shifting the source operand to the right N times.