Abstraction of spin-locks to support high performance computing

• US 10,691,487 B2
• Filed: 04/25/2018
• Issued: 06/23/2020
• Est. Priority Date: 04/25/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nilsen, Kelvin D.
• Primary Examiner(s): Wu, Qing Yuan
• Application Number:
  US15/962,187
• Publication Number:
  US 20190332446A1
• Time in Patent Office: 790 Days
• Field of Search: None
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/1479 Generic software techniques for error detection or fault masking
• CPC Class Codes: G06F 16/1774 Locking methods, e.g. locking methods for file systems allowing shared and concurrent access to files
• CPC Class Codes: G06F 2209/481 Exception handling
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/48 Program initiating; Program switching, e.g. by interrupt
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/4825 Interrupt from clock, e.g. time of day
• CPC Class Codes: G06F 9/524 Deadlock detection or avoidance
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A method comprises receiving a non-privileged disable interrupts instruction from a user application executing in user space, the non-privileged disable interrupts instruction having an operand with a non-zero value; determining a value in a special purpose register associated with disabling interrupts; and in response to determining that the value in the special purpose register associated with disabling interrupts is zero, disabling interrupts and placing the non-zero value of the operand in the special purpose register associated with disabling interrupts.

Claims

1. A method comprising:

receiving a non-privileged disable interrupts instruction from a user application executing in user space, the non-privileged disable interrupts instruction having an operand with a non-zero value;

determining a value in a special purpose register associated with disabling interrupts; and

in response to determining that the value in the special purpose register associated with disabling interrupts is zero, disabling interrupts and placing the non-zero value of the operand in the special purpose register associated with disabling interrupts.

2. The method of claim 1, further comprising:

receiving a non-privileged enable interrupts instruction from the user application executing in user space after disabling interrupts; and

in response to receiving the non-privileged enable interrupts instruction, enabling interrupts and resetting the special purpose register associated with disabling interrupts.

3. The method of claim 1, further comprising:

in response to determining that the value in the special purpose register associated with disabling interrupts is a non-zero value, raising an exception.

4. The method of claim 1, further comprising:

in response to placing the non-zero value of the operand in the special purpose register associated with disabling interrupts, executing a countdown timer, wherein executing the countdown timer comprises, for each clock cycle;

determining the value in the special purpose register associated with disabling interrupts;

in response to determining that the value in the special purpose register associated with disabling interrupts is non-zero, decrementing the value in the special purpose register associated with disabling interrupts; and

in response to determining that the value in the special purpose register associated with disabling interrupts is zero, enabling interrupts.

5. The method of claim 4, wherein executing the countdown timer further comprises:

in response to determining that the value in the special purpose register associated with disabling interrupts is zero, communicating a raised exception to a user.

6. The method of claim 1, wherein the value of the operand is an immediate mode operand having a predetermined bit size.

7. A method comprising:

executing a non-privileged disable interrupts instruction in user space to disable interrupts, wherein the non-privileged disable interrupts instruction has a non-zero operand value;

after executing the non-privileged disable interrupts instruction, executing a non-privileged spin-lock request in user space for a corresponding code segment;

in response to obtaining the spin-lock, executing the corresponding code segment;

in response to completing execution of the corresponding code segment, releasing the spin-lock; and

after releasing the spin-lock, executing a non-privileged enable interrupts instruction in user space to enable interrupts.

8. The method of claim 7, wherein executing the non-privileged disable interrupts instruction comprises:

disabling interrupts based on the non-zero operand value in the non-privileged disable interrupts instruction;

placing the non-zero operand value in a special purpose register associated with disabling interrupts; and

executing a countdown timer.

9. The method of claim 8, wherein executing the non-privileged enable interrupts instruction comprises:

enabling interrupts based on a zero operand value in the non-privileged enable interrupts instruction;

placing the zero operand value in the special purpose register associated with disabling interrupts; and

cancelling the countdown timer.

10. The method of claim 8, wherein executing the countdown timer comprises, for each clock cycle:

determining the value in the special purpose register associated with disabling interrupts;

in response to determining that the value in the special purpose register associated with disabling interrupts is non-zero, decrementing the value in the special purpose register associated with disabling interrupts; and

in response to determining that the value in the special purpose register associated with disabling interrupts is zero, enabling interrupts.

11. The method of claim 10, wherein executing the countdown timer further comprises:

in response to determining that the value in the special purpose register associated with disabling interrupts is zero, communicating a raised exception to a user.

12. The method of claim 7, wherein the non-privileged disable interrupts instruction expects an immediate mode operand having a predetermined bit size.

13. A processor core comprising:

a control unit configured to receive and decode a non-privileged disable interrupts instruction having an operand value which represents an estimate of an amount of time to disable interrupts; and

a plurality of registers, wherein one of the plurality of registers is a first special purpose register associated with the non-privileged disable interrupts instruction for storing the operand value from the non-privileged disable interrupts instruction.

14. The processor core of claim 13, further comprising circuitry associated with the first special purpose register and configured to periodically decrement the operand value stored in the first special purpose register.

15. The processor core of claim 14, wherein the circuitry associated with the first special purpose register is further configured to enable interrupts and raise an exception in response to determining that the operand value stored in the first special purpose register associated with the non-privileged disable interrupts instruction has been decremented to zero.

16. The processer core of claim 14, wherein the circuitry associated with the first special purpose register is configured to periodically decrement the operand value at a frequency scaled proportionally to a clock rate of a clock in the processor core.

17. The processor core of claim 16, further comprising:

a second special purpose register configured to store a value representative of an estimate of a number of central processing unit (CPU) time cycles consumed by a running thread; and

an oscillator associated with the second special purpose register and configured to trigger increments in the value stored in the second special purpose register at a frequency which is proportional to the clock rate of the clock;

wherein the circuitry associated with the first special purpose register is configured to decrement the value stored in the first special purpose register in lock-step with each increment of the second special purpose register.

18. A computer system comprising:

a memory configured to store a user application;

one or more processors communicatively coupled to the memory and configured to execute the user application in user space, each of the one or more processors having one or more cores;

wherein each of the one or more cores comprises;

a control unit configured to receive and decode a respective non-privileged disable interrupts instruction of the user application, the respective non-privileged disable interrupts instruction having a respective operand value which represents a respective estimate of an amount of time to disable interrupts; and

a plurality of registers, wherein one of the plurality of registers is a first special purpose register configured to store the operand value from the respective non-privileged disable interrupts instruction.

19. The computer system of claim 18, wherein each of the one or more processors is configured to:

determine the respective operand value in the respective non-privileged disable interrupts instruction;

in response to determining that the respective operand value is a non-zero value, determine a value in the first special purpose register; and

in response to determining that the value in the first special purpose register is zero, disable interrupts and place the non-zero operand value in the first special purpose register.

20. The computer system of claim 19, wherein each of the one or more processors is further configured to enable interrupts and place a zero value in the first special purpose register in response to receiving a respective non-privileged enable interrupts instruction.

21. The computer system of claim 18, wherein each of the one or more cores further comprises circuitry associated with the first special purpose register;

wherein, for each clock cycle, the circuitry associated with the first special purpose register is configured to;

determine the value in the first special purpose register;

in response to determining that the value in the first special purpose register is non-zero, decrement the value in the first special purpose register; and

in response to determining that the value in the first special purpose register is zero, enable interrupts.

22. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed by a processor, causes the processor to:

execute a non-privileged disable interrupts instruction in user space to disable interrupts, wherein the non-privileged disable interrupts instruction has a non-zero operand value;

execute a non-privileged spin-lock request in user space for a corresponding code segment after executing the non-privileged disable interrupts instruction;

in response to obtaining the spin-lock, execute the corresponding code segment;

in response to completing execution of the corresponding code segment, release the spin-lock; and

after releasing the spin-lock, execute a non-privileged enable interrupts instruction in user space to enable interrupts.

23. The computer program product of claim 22, wherein the computer readable program is further configured to cause the processor to execute the non-privileged disable interrupts instruction by:

disabling interrupts based on the non-zero operand value in the first non-privileged disable interrupts instruction;

placing the non-zero operand value in a special purpose register associated with disabling interrupts; and

executing a countdown timer.

24. The computer program product of claim 23, wherein the computer readable program is further configured to cause the processor to execute the non-privileged enable interrupts instruction by:

enabling interrupts;

resetting the special purpose register associated with disabling interrupts; and

cancelling the countdown timer.

25. The computer program product of claim 23, wherein the computer readable program is further configured to cause the processor to execute the countdown timer by, for each clock cycle:

determining the value in the special purpose register associated with disabling interrupts;

in response to determining that the value in the special purpose register associated with disabling interrupts is non-zero, decrementing the value in the special purpose register associated with disabling interrupts; and

in response to determining that the value in the special purpose register associated with disabling interrupts is zero, enabling interrupts.