Live error recovery

• US 10,691,520 B2
• Filed: 03/30/2018
• Issued: 06/23/2020
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jayaprakash Bharadwaj, Prahladachar, Brown, Alexander, Das Sharma, Debendra, Thaliyil, Junaid
• Primary Examiner(s): Nguyen, Thien
• Application Number:
  US15/942,186
• Publication Number:
  US 20180225167A1
• Time in Patent Office: 816 Days
• CPC Class Codes: G06F 11/0736 in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function testing or monitoring of automated control systems G05B23/02
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1415 at system level
• CPC Class Codes: G06F 11/1443 Transmit or communication errors
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

Claims

1. An apparatus comprising:

a capability structure associated with an downstream port error containment mode; and

a downstream port comprising;

input/output (I/O) circuitry to support communication with another device over a serial data link; and

error logic comprising hardware circuitry, wherein the error logic is to;

determine an uncorrectable error associated with a packet;

determine that a particular bit is set within the capability structure to indicate that the downstream port error containment mode is enabled for the downstream port, wherein the port error containment mode is to contain uncorrectable errors at the downstream port;

set a downstream port error containment status bit in a status register of the capability structure to trigger the downstream port error containment mode based at least in part on the particular bit set to indicate that the downstream port error containment mode is enabled;

halt traffic downstream from the downstream port in the downstream port error containment mode to avoid spread of data corruption associated with the uncorrectable error and to permit error recovery; and

detect that the downstream port error containment status bit is cleared;

wherein the I/O logic is to attempt to retrain the link based on clearing of the downstream port error containment status bit.

2. The apparatus of claim 1, wherein training sequences are to be sent on the link by the downstream port to force the link into a disabled link state and halt the traffic, and the traffic is to be halted without a reset of the downstream port.

3. The apparatus of claim 2, wherein the link is compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol.

4. The apparatus of claim 3, wherein the disabled state comprises a link state defined in the PCIe-based protocol.

5. The apparatus of claim 3, wherein the I/O logic comprises logic to implement a physical layer, data link layer, and transaction layer of the PCIe-based protocol.

6. The apparatus of claim 1, wherein the error logic is further to synthesize one or more completion packets in the downstream port error containment mode.

7. The apparatus of claim 1, wherein the error logic is to signal a correctable error to indicate the uncorrectable error instead of signaling an uncorrectable error within the downstream port error containment mode.

8. The apparatus of claim 7, wherein the correctable error is signaled based at least in part on a determination, by the error logic, that a correctable error signal control bit is set in a register.

9. The apparatus of claim 1, wherein a software-based manager is to attempt to recover the uncorrectable error while the downstream port error containment status bit is set.

10. The apparatus of claim 1, wherein the uncorrectable error comprises one of a fatal or non-fatal uncorrectable error.

11. The apparatus of claim 1, wherein software sets the particular bit to enable the downstream port error containment mode.

12. The apparatus of claim 1, wherein the error logic is to report the uncorrectable error.

13. The apparatus of claim 1, further comprising switching circuitry.

14. The apparatus of claim 13, wherein the apparatus comprises a switch.

15. The apparatus of claim 1, wherein the downstream port error containment status bit is cleared by software.

16. A method comprising:

receiving, over an interconnect, a packet at a device;

detecting, at a downstream port of the device, an uncorrectable error associated with the packet;

determining, from a particular bit in an extended capability structure of the device, that a downstream port error containment mode is enabled for the downstream port, wherein the downstream port error containment mode is to contain uncorrectable errors at the downstream port;

setting a downstream port error containment status bit in a status register of the extended capability structure to trigger the downstream port error containment mode based the downstream port error containment mode being enabled;

halting traffic downstream from the downstream port in the downstream port error containment mode to avoid spread of data corruption associated with the error and to permit error recovery, wherein halting the traffic comprises sending training sequences on the link by the downstream port to force the link into a disabled link state, and the traffic is to be halted without a reset of the device;

detecting that the downstream port error containment status bit is cleared; and

attempting to retrain the link based on clearing of the downstream port error containment status bit.

17. A switch device comprising:

memory comprising a capability structure associated with a downstream port error containment mode;

switching circuitry;

error logic comprising hardware circuitry, wherein the error logic is to;

determine an uncorrectable error associated with a packet;

determine that a particular bit is set within the capability structure to indicate that the downstream port error containment mode is enabled for the downstream port, wherein the port error containment mode is to contain uncorrectable errors at the downstream port;

set a downstream port error containment status bit in a status register of the capability structure to trigger the downstream port error containment mode based at least in part on the particular bit set to indicate that the downstream port error containment mode is enabled;

halt traffic downstream from the downstream port in the downstream port error containment mode to avoid spread of data corruption associated with the uncorrectable error and to permit error recovery, wherein training sequences are to be sent on the link by the downstream port to force the link into a disabled link state and halt the traffic, and the traffic is to be halted without a reset of the downstream port; and

detect that the downstream port error containment status bit is cleared; and

link training logic to retrain the link based on clearing of the downstream port error containment status bit.

18. A system comprising:

a first device; and

a second device connected to the first device by a serial data link, wherein the second device comprises;

a capability structure associated with a downstream port error containment mode; and

a downstream port, wherein the downstream port comprises hardware-implemented logic comprising;

input/output (I/O) logic to support communication on the serial data link with the first device;

error logic to;

determine an uncorrectable error associated with a packet;

determine that a particular bit is set within the capability structure to indicate that the downstream port error containment mode is enabled for the downstream port, wherein the port error containment mode is to contain uncorrectable errors at the downstream port;

set a downstream port error containment status bit in a status register of the extended capability structure to trigger the downstream port error containment mode based at least in part on the particular bit set to indicate that the downstream port error containment mode is enabled;

halt traffic downstream from the downstream port in the downstream port error containment mode to avoid spread of data corruption associated with the error and to permit error recovery, wherein training sequences are to be sent on the link by the downstream port to force the link into a disabled link state and halt the traffic, and the traffic is to be halted without a reset of the downstream port; and

detect that the downstream port error containment status bit is cleared by software,

wherein the I/O logic is to attempt to retrain the link based on clearing of the downstream port error containment status bit.

19. The system of claim 18, wherein the first device comprises a processor device.

20. The system of claim 18, wherein the second device comprises a switch device.

21. The system of claim 18, wherein the second device comprises a bridge device.

22. The system of claim 18, wherein the second device comprises a root port.

23. A system comprising:

means for receiving a packet on an interconnect, wherein the interconnect couples a set of devices in a computer;

means for detecting, at a downstream port of a particular one of the set of devices, an uncorrectable error associated with a packet;

means for determining, from a particular bit in an extended capability structure of the device, that a downstream port error containment mode is enabled for the downstream port, wherein the downstream port error containment mode is to contain uncorrectable errors at the downstream port;

means for setting a downstream port error containment status bit in a status register of the extended capability structure to trigger the downstream port error containment mode based the downstream port error containment mode being enabled;

means for halting traffic downstream from the downstream port in the downstream port error containment mode to avoid spread of data corruption associated with the error and to permit error recovery, wherein halting the traffic comprises sending training sequences on the link by the downstream port to force the link into a disabled link state, and the traffic is to be halted without a reset of the device;

means for detecting that the downstream port error containment status bit is cleared; and

means for attempting to retrain the link based on clearing of the downstream port error containment status bit.