Data cache segregation for spectre mitigation
First Claim
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1. A device comprising:
- at least one central processing unit (CPU) core comprising;
at least a first CPU thread;
at least a first L1 cache accessible to the first CPU thread;
plural signal lines for communicating data between the first CPU thread and the first L1 cache, the CPU thread being configured to expose a binary value on at least a mode signal line of the plural signal lines, a first binary value on the mode signal line indicating a memory address associated only with kernel mode cache, a second binary value on the mode signal line indicating a memory address associated only with user mode cache, wherein data associated with a user mode application can be written to and read from only user mode cache such that no user mode application can detect operations of the kernel mode cache.
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Abstract
The data cache of a processor is segregated by execution mode, eliminating the danger of certain malware by no longer sharing the resource. Kernel-mode software can adjust the relative size of the two portions of the data cache, to dynamically accommodate the data-cache needs of varying workloads.
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Citations
20 Claims
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1. A device comprising:
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at least one central processing unit (CPU) core comprising; at least a first CPU thread; at least a first L1 cache accessible to the first CPU thread; plural signal lines for communicating data between the first CPU thread and the first L1 cache, the CPU thread being configured to expose a binary value on at least a mode signal line of the plural signal lines, a first binary value on the mode signal line indicating a memory address associated only with kernel mode cache, a second binary value on the mode signal line indicating a memory address associated only with user mode cache, wherein data associated with a user mode application can be written to and read from only user mode cache such that no user mode application can detect operations of the kernel mode cache. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus comprising:
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at least one central processing unit (CPU) core comprising; at least a first CPU thread; an L1 cache assembly accessible to the first CPU thread; and plural signal lines for communicating data between the first CPU thread and the L1 cache assembly, the CPU thread being configured to expose a binary value on at least a mode signal line of the plural signal lines, a first binary value on the mode signal line indicating a memory address associated with a kernel mode cache of the L1 cache assembly a second binary value on the mode signal line indicating a memory address associated with a user mode cache of the L1 cache assembly. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A method, comprising:
- segregating data cache of a processor according to execution mode, execution mode comprising kernel mode and user mode; and
exposing a binary value on at least a first signal line of plural signal lines, a first binary value on the mode signal line indicating a memory address associated with the kernel mode, a second binary value on the first signal line indicating a memory address associated with the user mode. - View Dependent Claims (20)
- segregating data cache of a processor according to execution mode, execution mode comprising kernel mode and user mode; and
Specification