Die and package

• US 10,691,634 B2
• Filed: 11/30/2015
• Issued: 06/23/2020
• Est. Priority Date: 11/30/2015
• Status: Active Grant

• Current Assignee: PEZY Computing K.K.
• Original Assignee: PEZY Computing K.K.
• Inventors: Saito, Motoaki
• Primary Examiner(s): Ojha, Ajay
• Application Number:
  US15/780,070
• Publication Number:
  US 20180365192A1
• Time in Patent Office: 1,667 Days
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/7807 System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
• CPC Class Codes: G06F 15/7896 Modular architectures, e.g. assembled from a number of identical packages
• CPC Class Codes: G06F 15/803 Three-dimensional arrays or hypercubes
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

Provided efficiently and at low cost are: a package for core number ratios appropriate for all types of computers; and dies included in the package.

This package includes at least one die provided with: at least one of a first core formed of a CPU core or a latency core and a second core formed of an accelerator core or a throughput core; an external interface; memory interfaces 24 to 26; and a die interface 23 which is connected to another die.

The die includes a first type die and a second type die each including both the first core and the second core and the core number ratio between the first core and the second core in the first type die differs from that in the second type die.

Moreover, the memory interfaces include an interface conforming to TCI.

In addition, the memory interfaces further include an interface conforming to HBM.

Claims

1. A set of dies, each die including:

at least one of a first core and a second core, the first core being a CPU or a latency core, and the second core being an accelerator core or a throughput core, and

an external interface,

one or more types of memory interfaces, and

a die interface for connecting to another die,

wherein the set of dies comprises;

a first die comprising at least both the first core and the second core;

a second die comprising at least both the first core and the second core; and

one or more third dies comprising one of the first core and the second core,

wherein if the interfaces are provided along two adjacent sides of an arbitrary die selected from the set of dies, the interfaces being different interfaces or different types of memory interfaces are arranged on the two adjacent sides, or

wherein if instead the interfaces are provided along two opposite sides of an arbitrary die selected from the set of dies, the interfaces being different interfaces or same first type memory interfaces are arranged on the two opposite sides, wherein one of the different interfaces is provided with the die interface, and the other is provided with a second type memory interface.

2. The set of dies according to claim 1,

wherein the one or more types of memory interfaces include an interface conforming to specifications for performing communication in an electrically non-contact manner.

3. The set of dies according to claim 2,

wherein the one or more types of memory interfaces include an interface conforming to TCI.

4. The set of dies according to claim 2,

wherein the one or more types of memory interfaces further include an interface conforming to a three-dimensional stacked next-generation high-speed memory that performs communication in an electrically contact manner.

5. The set of dies according to claim 4,

wherein the one or more types of memory interfaces further include an interface conforming to HBM.

6. The set of dies according to claim 1,

wherein the one or more types of memory interfaces include an interface conforming to a general-purpose memory performing communication in an electrically contact manner and a DIMM (dual inline memory module).

7. The set of dies according to claim 6,

wherein the one or more types of memory interfaces further include an interface conforming to DDR4.

8. A package including at least one die of the set of dies according to claim 1.

9. The package according to claim 8,

further comprising

memories connected to the one or more types of memory interfaces of the at least one die of the set of dies.

10. The package according to claim 9,

wherein the one or more types of memory interfaces include an interface conforming to specifications for performing communication in an electrically non-contact manner.

11. The package according to claim 10,

wherein the one or more types of memory interfaces include an interface conforming to TCI.

12. The package according to claim 10,

wherein the one or more types of memory interfaces further include an interface conforming to a three-dimensional stacked next-generation high-speed memory that performs communication in an electrically contact manner.

13. The package according to claim 12,

wherein the one or more types of memory interfaces further include an interface conforming to HBM.

14. The package according to claim 8,

wherein the package includes at least one die of the first die and the second die,

wherein the package further includes the one or more third dies including memory interfaces conforming to a general-purpose memory performing communication in an electrically contact manner and a DIMM (dual inline memory module), and

the at least one die and the one or more third dies die are mutually connected by the respective die interfaces.

15. The set of dies according to claim 1,

wherein a core number ratio between the first core and the second core is different in each die selected from the set of dies.