Encryption for XIP and MMIO external memories

• US 10,691,838 B2
• Filed: 12/20/2018
• Issued: 06/23/2020
• Est. Priority Date: 06/20/2014
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Van Antwerpen, Hans, Van de Waerdt, Jan-Willem
• Primary Examiner(s): Poltorak, Piotr
• Application Number:
  US16/228,057
• Publication Number:
  US 20190122007A1
• Time in Patent Office: 551 Days
• Field of Search: None
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2213/0016 Inter-integrated circuit (I2C)
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Techniques for multiplexing between an execute-in-place (XIP) mode and a memory-mapped input/output (MMIO) mode for access to external memory devices are described herein. In an example embodiment, an IC device comprises a serial interface and a controller that is configured to communicate with external memory devices over the serial interface. The controller comprises a control register and a cryptography block. The control register is configured to indicate an XIP mode or a MMIO mode. Caches in XIP interfaces provide seamless access to multiple memories, or multiple portions of a single memory. The cryptography block is configured to encrypt and decrypt XIP data transfers to and from a first external memory device in the XIP mode, and to encrypt and decrypt MMIO data transfers to and from a second external memory device in the MMIO mode.

Claims

1. An integrated circuit (IC) device comprising:

a serial interface;

an interconnect bus; and

a controller coupled to the serial interface and configured to communicate with at least one external memory device over the serial interface, wherein the controller comprises;

a first execute-in-place (XIP) interface coupled to the interconnect bus, the first XIP interface including a first cache and configured to communicate at a first speed;

a second XIP interface coupled to the serial interface coupled to the interconnect bus, the second XIP interface including a second cache and configured to communicate at a second speed.

2. The IC device of claim 1, wherein the controller further comprises an MMIO interface coupled to the interconnect bus.

3. The IC device of claim 2 wherein, in both an XIP mode and an MMIO mode, data blocks are transferred to and stored in the at least one external memory device in an encrypted form.

4. The IC device of claim 2, wherein the controller further comprises an MMIO block that includes MMIO registers, and wherein:

in an XIP mode, the MMIO registers are configured to store an address for the XIP data transfer; and

in an MMIO mode, the MMIO registers are configured to store a data block of the MMIO data transfer.

5. The IC device of claim 1, wherein the first cache is for storing data transfers to a first portion of the at least one external memory device and the second cache is for storing data transfers to a second portion of the at least one external memory device.

6. The IC device of claim 5, wherein the controller is configured with an XIP address space and an MMIO address space, and wherein:

the XIP address space includes addresses that are mapped directly to first external memory locations; and

the MMIO address space includes addresses that are mapped to MMIO registers, wherein the MMIO registers are mapped to second external memory locations.

7. The IC device of claim 1, wherein the first speed is faster than the second speed.

8. The IC device of claim 7, further comprising an interconnect bus, wherein the controller further comprises a port arbitration block configured to priority arbitrate the XIP data transfers between the first XIP interface and the second XIP interface.

9. The IC device of claim 1, wherein the controller is further configured to perform an initialization operation that programs a control register to a first value that indicates an XIP mode or to a second value that indicates an MMIO mode.

10. The IC device of claim 1, wherein the controller further comprises first-in-first-out (FIFO) queues that are shared between an XIP mode and an MMIO mode.

11. A system comprising:

a plurality of memory devices comprising a first memory device and a second memory device; and

a microcontroller external to the plurality of memory devices, the microcontroller comprising;

a serial interface, the serial interface coupled to the microcontroller and to the plurality of memory devices;

an interconnect bus; and

an external memory controller, the external memory controller coupled between the serial interface and the interconnect bus, wherein the external memory controller comprises;

a control register configured to indicate an execute-in-place (XIP) mode or a memory-mapped input/output (MMIO) mode; and

a first execute-in-place (XIP) interface coupled to the interconnect bus, the first XIP interface including a first cache and configured to communicate at a first speed;

a second XIP interface coupled to the serial interface coupled to the interconnect bus, the second XIP interface including a second cache and configured to communicate at a second speed.

12. The system of claim 11, wherein the external memory controller is configured with a XIP address space and a MMIO address space, and wherein:

the XIP address space includes addresses that are mapped directly to first external memory locations; and

the MMIO address space includes addresses that are mapped to MMIO registers, wherein the MMIO registers are mapped to second external memory locations.

13. The system of claim 12, wherein the first external memory locations include first sub-locations assigned to the first XIP interface and second sub-locations assigned to the second XIP interface.

14. The system of claim 12, wherein the first XIP interface is a fast XIP interface and the second XIP interface is a slow XIP interface.

15. The system of claim 14, wherein the external memory controller comprises a port arbitration block configured to priority arbitrate the XIP data transfers between the fast XIP interface and the slow XIP interface.

16. The system of claim 11 wherein, in both an XIP mode and an MMIO mode, data blocks are transferred to and stored in the first and second memory devices in encrypted form.

17. The system of claim 11, wherein the external memory controller further comprises:

an XIP block configured to automatically translate the XIP data transfers to serial data transfers on the serial interface, in the XIP mode;

first-in-first-out (FIFO) queues coupled to the serial interface; and

a MMIO block coupled to the FIFO queues and configured to use the FIFO queues to construct serial interface transfers for the MMIO data transfers, in the MMIO mode.

18. The system of claim 11, wherein the external memory controller is further configured to perform an initialization operation that programs a control register to a first value that indicates the XIP mode or to a second value that indicates the MMIO mode.

19. The system of claim 18, wherein the external memory controller further comprises a mode multiplexer block configured to provide access to the serial interface at any one time either in the XIP mode or in the MMIO mode, based on the control register.

20. The system of claim 11, wherein the external memory controller further comprises first-in-first-out (FIFO) queues that are shared between an XIP mode and an MMIO mode.