Encryption for XIP and MMIO external memories
First Claim
1. An integrated circuit (IC) device comprising:
- a serial interface;
an interconnect bus; and
a controller coupled to the serial interface and configured to communicate with at least one external memory device over the serial interface, wherein the controller comprises;
a first execute-in-place (XIP) interface coupled to the interconnect bus, the first XIP interface including a first cache and configured to communicate at a first speed;
a second XIP interface coupled to the serial interface coupled to the interconnect bus, the second XIP interface including a second cache and configured to communicate at a second speed.
3 Assignments
0 Petitions
Accused Products
Abstract
Techniques for multiplexing between an execute-in-place (XIP) mode and a memory-mapped input/output (MMIO) mode for access to external memory devices are described herein. In an example embodiment, an IC device comprises a serial interface and a controller that is configured to communicate with external memory devices over the serial interface. The controller comprises a control register and a cryptography block. The control register is configured to indicate an XIP mode or a MMIO mode. Caches in XIP interfaces provide seamless access to multiple memories, or multiple portions of a single memory. The cryptography block is configured to encrypt and decrypt XIP data transfers to and from a first external memory device in the XIP mode, and to encrypt and decrypt MMIO data transfers to and from a second external memory device in the MMIO mode.
-
Citations
20 Claims
-
1. An integrated circuit (IC) device comprising:
-
a serial interface; an interconnect bus; and a controller coupled to the serial interface and configured to communicate with at least one external memory device over the serial interface, wherein the controller comprises; a first execute-in-place (XIP) interface coupled to the interconnect bus, the first XIP interface including a first cache and configured to communicate at a first speed; a second XIP interface coupled to the serial interface coupled to the interconnect bus, the second XIP interface including a second cache and configured to communicate at a second speed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A system comprising:
-
a plurality of memory devices comprising a first memory device and a second memory device; and a microcontroller external to the plurality of memory devices, the microcontroller comprising; a serial interface, the serial interface coupled to the microcontroller and to the plurality of memory devices; an interconnect bus; and an external memory controller, the external memory controller coupled between the serial interface and the interconnect bus, wherein the external memory controller comprises; a control register configured to indicate an execute-in-place (XIP) mode or a memory-mapped input/output (MMIO) mode; and a first execute-in-place (XIP) interface coupled to the interconnect bus, the first XIP interface including a first cache and configured to communicate at a first speed; a second XIP interface coupled to the serial interface coupled to the interconnect bus, the second XIP interface including a second cache and configured to communicate at a second speed. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
Specification