Filing vacant areas of an integrated circuit design

• US 10,691,858 B1
• Filed: 09/19/2017
• Issued: 06/23/2020
• Est. Priority Date: 03/18/2009
• Status: Active Grant

• Current Assignee: Pulsic Limited
• Original Assignee: Pulsic Limited
• Inventors: Balsdon, Graham
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): Bowers, Brandon
• Application Number:
  US15/709,376
• Time in Patent Office: 1,008 Days
• Field of Search: 716118
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.

Claims

1. A method comprising:

using a computer, automatically creating a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design;

finding a second shape and a third shape on a second layer of the integrated circuit design that both overlap the first shape, wherein the second layer is different from the first layer;

determining the second shape is coupled to a first power net and the third shape is coupled to a second power net, different from the first power net;

making a determination whether to couple the first shape to the second shape or the third shape based on target percentages specified for the first and second power nets;

if the determination is made to couple the first shape to the second shape, automatically creating a first via shape in a third layer, different from the first and second layers, that overlaps both the first and second shapes; and

if the determination is made to couple the first shape to the third shape, automatically creating a second via shape in the third layer that overlaps both the first and third shapes.

2. The method of claim 1 wherein the making a determination whether to couple the first shape to the second shape or the third shape based on target percentages specified for the first and second power nets comprises:

determining a first percentage utilization of the first power net in the free space and a second percentage utilization of the second power net in the free space; and

determining whether the first percentage utilization is less than a target percentage for the first power net and the second percentage utilization is less than a target percentage for the second power net.

3. The method of claim 1 comprising:

forming an integrated circuit from the integrated circuit design.

4. The method of claim 1 comprising:

forming at least one photolithography mask that is used for the fabrication of an integrated circuit represented by the integrated circuit design.

5. The method of claim 1 comprising:

upon request by a user, showing only the automatically generated shapes of the first layer on a display of the computer.

6. The method of claim 1 comprising:

upon request by a user, showing only the automatically generated shapes of the third layer on a display of the computer.

7. The method of claim 1 wherein a distance from a leftmost edge of the first shape to a rightmost edge of the first shape does not exceed a maximum width specified for the automatic creation.

8. The method of claim 1 wherein the automatically creating a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design comprises:

determining where the first rectangle overlaps a previously drawn second rectangle on the first layer;

using at least one computer processor, oversizing the second rectangle to obtain a third rectangle;

using at least one computer processor, subtracting the third rectangle from the first rectangle to form a fourth rectangle, fifth rectangle, and sixth rectangle, wherein the fourth, fifth, and sixth rectangles each have a smaller area than the first rectangle and the fourth, fifth, and sixth rectangles overlap;

if the sixth rectangle has a smaller width than a first minimum width, discarding the sixth rectangle while keeping the fourth and fifth rectangles;

starting with an edge of the fourth rectangle, growing an island that extends from the edge to a limit line at a second minimum width; and

discarding portions of the fourth and fifth rectangles beyond the limit line to obtain a first shape comprising rectangles.

9. The method of claim 1 wherein the first power net is a first supply voltage.

10. The method of claim 9 wherein the second power net is ground.

11. The method of claim 1 comprising at least one of

forming an integrated circuit from the integrated circuit design, or

forming at least one photolithography mask that is used for the fabrication of an integrated circuit represented by the integrated circuit design.

12. A method comprising:

using a computer, automatically creating a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design, wherein the automatically creating a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design comprises;

determining where the first rectangle overlaps a previously drawn second rectangle on the first layer;

using at least one computer processor, oversizing the second rectangle to obtain a third rectangle;

using at least one computer processor, subtracting the third rectangle from the first rectangle to form a fourth rectangle, fifth rectangle, and sixth rectangle, wherein the fourth, fifth, and sixth rectangles each have a smaller area than the first rectangle and the fourth, fifth, and sixth rectangles overlap;

if the sixth rectangle has a smaller width than a first minimum width, discarding the sixth rectangle while keeping the fourth and fifth rectangles;

starting with an edge of the fourth rectangle, growing an island that extends from the edge to a limit line at a second minimum width; and

discarding portions of the fourth and fifth rectangles beyond the limit line to obtain a first shape comprising rectangles;

finding a second shape and a third shape on a second layer of the integrated circuit design that both overlap the first shape, wherein the second layer is different from the first layer;

determining the second shape is coupled to a first power net and the third shape is coupled to a second power net, different from the first power net;

making a determination whether to couple the first shape to the second shape or the third shape based on target percentages specified for the first and second power nets, wherein the making a determination whether to couple the first shape to the second shape or the third shape based on target percentages specified for the first and second power nets comprises;

determining a first percentage utilization of the first power net in the free space and a second percentage utilization of the second power net in the free space; and

determining whether the first percentage utilization is less than a target percentage for the first power net and the second percentage utilization is less than a target percentage for the second power net;

if the determination is made to couple the first shape to the second shape, automatically creating a first via shape in a third layer, different from the first and second layers, that overlaps both the first and second shapes; and

if the determination is made to couple the first shape to the third shape, automatically creating a second via shape in the third layer that overlaps both the first and third shapes.

13. The method of claim 12 comprising:

forming an integrated circuit from the integrated circuit design.

14. The method of claim 12 comprising:

forming at least one photolithography mask that is used for the fabrication of an integrated circuit represented by the integrated circuit design.

15. The method of claim 12 comprising:

upon request by a user, showing only the automatically generated shapes of the first layer on a display of the computer.

16. The method of claim 12 comprising:

upon request by a user, showing only the automatically generated shapes of the third layer on a display of the computer.

17. The method of claim 12 wherein a distance from a leftmost edge of the first shape to a rightmost edge of the first shape does not exceed a maximum width specified for the automatic creation.

18. The method of claim 12 wherein the first power net is a first supply voltage.

19. The method of claim 18 wherein the second power net is ground.

20. A method comprising:

using a computer, automatically creating a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design, wherein a distance from a leftmost edge of the first shape to a rightmost edge of the first shape does not exceed a maximum width specified for the automatic creation, and the automatically creating a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design comprises;

determining where the first rectangle overlaps a previously drawn second rectangle on the first layer;

using at least one computer processor, oversizing the second rectangle to obtain a third rectangle;

using at least one computer processor, subtracting the third rectangle from the first rectangle to form a fourth rectangle, fifth rectangle, and sixth rectangle, wherein the fourth, fifth, and sixth rectangles each have a smaller area than the first rectangle and the fourth, fifth, and sixth rectangles overlap;

if the sixth rectangle has a smaller width than a first minimum width, discarding the sixth rectangle while keeping the fourth and fifth rectangles;

starting with an edge of the fourth rectangle, growing an island that extends from the edge to a limit line at a second minimum width; and

discarding portions of the fourth and fifth rectangles beyond the limit line to obtain a first shape comprising rectangles;

finding a second shape and a third shape on a second layer of the integrated circuit design that both overlap the first shape, wherein the second layer is different from the first layer;

determining the second shape is coupled to a first power net and the third shape is coupled to a second power net, wherein the first power net is a first supply voltage and the second power net is ground;

making a determination whether to couple the first shape to the second shape or the third shape based on target percentages specified for the first and second power nets, wherein the making a determination whether to couple the first shape to the second shape or the third shape based on target percentages specified for the first and second power nets comprises;

determining a first percentage utilization of the first power net in the free space and a second percentage utilization of the second power net in the free space; and

determining whether the first percentage utilization is less than a target percentage for the first power net and the second percentage utilization is less than a target percentage for the second power net;

if the determination is made to couple the first shape to the second shape, automatically creating a first via shape in a third layer, different from the first and second layers, that overlaps both the first and second shapes; and

if the determination is made to couple the first shape to the third shape, automatically creating a second via shape in the third layer that overlaps both the first and third shapes.