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Filing vacant areas of an integrated circuit design

  • US 10,691,858 B1
  • Filed: 09/19/2017
  • Issued: 06/23/2020
  • Est. Priority Date: 03/18/2009
  • Status: Active Grant
First Claim
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1. A method comprising:

  • using a computer, automatically creating a first shape comprising rectangles that is representative of free space on a first layer of an integrated circuit design;

    finding a second shape and a third shape on a second layer of the integrated circuit design that both overlap the first shape, wherein the second layer is different from the first layer;

    determining the second shape is coupled to a first power net and the third shape is coupled to a second power net, different from the first power net;

    making a determination whether to couple the first shape to the second shape or the third shape based on target percentages specified for the first and second power nets;

    if the determination is made to couple the first shape to the second shape, automatically creating a first via shape in a third layer, different from the first and second layers, that overlaps both the first and second shapes; and

    if the determination is made to couple the first shape to the third shape, automatically creating a second via shape in the third layer that overlaps both the first and third shapes.

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