Method for programming a memory circuit with a verification process

• US 10,692,546 B2
• Filed: 02/26/2019
• Issued: 06/23/2020
• Est. Priority Date: 04/18/2018
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Hoang, Dung Le Tan
• Primary Examiner(s): Le, Thong Q
• Application Number:
  US16/285,218
• Publication Number:
  US 20190325977A1
• Time in Patent Office: 483 Days
• Field of Search: 365154, 365194, 365203, 36518905, 365205, 365 4917, 36518917, 3652101
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: H01L 21/02107 Forming insulating materials on a substrate
• CPC Class Codes: H01L 21/02109 characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
• CPC Class Codes: H01L 21/02112 characterised by the material of the layer
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02225 characterised by the process for the formation of the insulating layer
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/0226 formation by a deposition process per se C23C
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 : the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/408 : with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Abstract

A memory circuit includes a memory cell, a first program driver, a second program driver, and a sensing amplifier. A method for operating the memory circuit includes, during a program operation of the memory cell, providing a program voltage to the memory cell, enabling the first program driver to drive the first local bit line to be at a low voltage, enabling the second program driver, disabling the first program driver, and enabling the sensing amplifier to verify whether the first memory cell has been programmed or not. The second program driver has a weaker driving ability than the first program driver.

Claims

1. A memory circuit comprising:

a first memory cell coupled to a first local bit line, and comprising an antifuse transistor configured to receive a program voltage during a program operation of the first memory cell;

a first program driver coupled to the first local bit line, and configured to drive the first local bit line to be at a low voltage when being enabled during the program operation of the first memory cell;

a second program driver coupled to the first local bit line, and configured to drive the first local bit line to be close to the low voltage when being enabled during the program operation of the first memory cell, wherein the second program driver has a weaker driving ability than the first program driver;

a sensing amplifier coupled to the first local bit line, and configured to verify whether the first memory cell has been programmed or not by comparing a verification reference voltage and a bit line voltage on the first local bit line caused by a current generated by the first memory cell when being enabled during the program operation of the first memory cell; and

a program control circuit coupled to the first program driver, the second program driver, and the sensing amplifier driver, and configured to;

enable the first program driver and the second program driver during the program operation;

disable the first program driver after the first program driver is enabled for a predetermined time; and

enable the sensing amplifier after the first program driver is disabled during the program operation.

2. The memory circuit of claim 1, wherein the program control circuit is further configured to terminate the program operation by disabling the first program driver and the second program driver when the sensing amplifier verifies that the first memory cell has been programmed.

3. The memory circuit of claim 2, wherein the program control circuit is further configured to disable a charge pump configured to provide the program voltage when the sensing amplifier verifies that the first memory cell has been programmed.

4. The memory circuit of claim 1, wherein the program control circuit is further configured to enable the first program driver again when the sensing amplifier verifies that the first memory cell has not been programmed.

5. The memory circuit of claim 1, wherein the first program driver comprises:

a first NAND gate having a first input terminal configured to receive a first enable signal, a second input terminal, and an output terminal;

a first inverter having an input terminal configured to receive a program verification signal, and an output terminal coupled to the second input terminal of the first NAND gate;

a second NAND gate having a first input terminal configured to receive a program control signal, a second input terminal coupled to the output terminal of the first NAND gate, and an output terminal;

a second inverter having an input terminal configured to receive the program control signal, and an output terminal;

a NOR gate having a first input terminal coupled to the output terminal of the first NAND gate, a second input terminal coupled to the output terminal of the second inverter, and an output terminal;

a P-type transistor having a first terminal configured to receive a first system voltage, a second terminal coupled to the first local bit line, and a control terminal coupled to the output terminal of the second NAND gate; and

an N-type transistor having a first terminal coupled to the second terminal of the P-type transistor, a second terminal configured to receive a second system voltage lower than the first system voltage, and a control terminal coupled to the output terminal of the NOR gate.

6. The memory circuit of claim 5, wherein:

the first enable signal and the program verification signal are generated by the program control circuit;

the first enable signal is a clock signal switching between a low operation voltage and a high operation voltage; and

the program verification signal has a high voltage pulse when the first enable signal changes from the low operation voltage to the high operation voltage during the program operation of the first memory cell.

7. The memory circuit of claim 6, wherein:

the program control circuit further generates a sensing pulse signal to enable the sensing amplifier; and

the sensing pulse signal starts after a rising edge of the high voltage pulse of the program verification signal and terminates no later than a falling edge of the high voltage pulse.

8. The memory circuit of claim 1, wherein the second program driver comprises a current source.

9. The memory circuit of claim 1, wherein:

the sensing amplifier is further configured to determine a data value stored in the first memory cell by comparing a read reference voltage and the bit line voltage on the first local bit line when being enabled during a read operation of the first memory cell.

10. The memory circuit of claim 1, further comprising:

a second memory cell coupled to a second local bit line, and comprising a antifuse transistor configured to receive the program voltage during a program operation of the second memory cell; and

an address decoder coupled to the first local bit line, the second local bit line, and a main bit line, and configured to form an electrical connection between the first local bit line and the main bit line during the program operation of the first memory cell, and form an electrical connection between the second local bit line and the main bit line during the program operation of the second memory cell;

wherein the first program driver and the second program driver are coupled to the first local bit line and the second local bit line through the main bit line.

11. The memory circuit of claim 1, wherein the second program driver remains enabled during the program operation after being enabled.

12. The memory circuit of claim 1, wherein the second program driver is enabled when the first program driver is disabled during the program operation, and is disabled when the first program driver is enabled.