Method and device for electrical overstress and electrostatic discharge protection

• US 10,692,854 B2
• Filed: 03/19/2018
• Issued: 06/23/2020
• Est. Priority Date: 03/28/2017
• Status: Active Grant

• Current Assignee: Semtech Corporation
• Original Assignee: Semtech Corporation
• Inventors: Rose, David J., Russell, William A., Clark, Jonathan
• Primary Examiner(s): Comber, Kevin J
• Application Number:
  US15/925,569
• Publication Number:
  US 20180286854A1
• Time in Patent Office: 827 Days
• Field of Search: 361 56, 361119
• CPC Class Codes: H01C 7/12 Overvoltage protection resistors series resistors structurally associated with spark gaps H01T1/16
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H02H 9/025 Current limitation using field effect transistors
• CPC Class Codes: H02H 9/041 using a short-circuiting device
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

A semiconductor device is protected from electrical overstress (EOS) and electro-static discharge (ESD) events by a series protection circuit electrically coupled in series along the transmission line between a signal source and a load. The series protection circuit includes a first field-effect transistor (FET) electrically coupled in series between the signal source and load. A parallel protection circuit is electrically coupled between the transmission line and a ground node. The parallel protection circuit can include a transient-voltage-suppression (TVS) diode.

Claims

1. A semiconductor device, comprising:

a signal source;

a load;

a transmission line coupled between the signal source and load;

a series protection circuit electrically coupled in series along the transmission line between the signal source and the load, wherein the series protection circuit includes,

a junction field-effect transistor (JFET), and

a resistor disposed between the JFET and load, wherein the JFET, resistor, and transmission line are electrically coupled in series between the signal source and load; and

a parallel protection circuit electrically coupled between the transmission line and a ground node, wherein the parallel protection circuit is directly coupled to a gate terminal of the JFET.

2. The semiconductor device of claim 1, wherein the parallel protection circuit includes a transient-voltage-suppression (TVS) diode.

3. The semiconductor device of claim 1, wherein a conduction terminal of the JFET is directly coupled to a first terminal of the resistor and the gate terminal of the JFET is directly coupled to a second terminal of the resistor.

4. A semiconductor device, comprising:

a signal source;

a load;

a series protection circuit including a junction field-effect transistor (JFET) and a resistor electrically coupled in series between the signal source and the load, wherein a conduction terminal of the JFET is directly coupled to a first terminal of the resistor and a gate terminal of the JFET is directly coupled to a second terminal of the resistor; and

a parallel protection circuit electrically coupled between the load and a ground node, wherein the gate terminal of the JFET is directly coupled to the parallel protection circuit.

5. The semiconductor device of claim 4, wherein the series protection circuit and parallel protection circuit are disposed within a single semiconductor package.

6. A method of making a semiconductor device, comprising:

providing a junction field-effect transistor (JFET);

providing a resistor electrically coupled in series with the JFET between a signal source and a signal destination of the semiconductor device, wherein a conduction terminal of the JFET is coupled to a first terminal of the resistor and a gate terminal of the JFET is coupled to a second terminal of the resistor;

providing a parallel protection circuit electrically coupled to the series protection circuit; and

electrically coupling the parallel protection circuit directly to a gate terminal of the JFET.

7. The method of claim 6, wherein providing the parallel protection circuit includes providing a transient-voltage-suppression (TVS) diode.

8. The method of claim 6, wherein the series protection circuit and parallel protection circuit are packaged together.

9. The method of claim 6, wherein the parallel protection circuit is coupled to a ground node.

10. An electronic device, comprising:

a series protection circuit electrically coupled in series between a load within the electronic device and a signal source external to the electronic device, wherein the series protection circuit includes,

a junction field-effect transistor (JFET), and

a resistor electrically coupled in series with the JFET between the signal source and load, wherein a conduction terminal of the JFET is coupled to a first terminal of the resistor and a gate terminal of the JFET is coupled to a second terminal of the resistor; and

a parallel protection circuit electrically coupled between the series protection circuit and a voltage node, wherein a gate terminal of the JFET is directly coupled to the parallel protection circuit.

11. The electronic device of claim 10, wherein the parallel protection circuit includes a transient-voltage-suppression (TVS) diode.

12. The electronic device of claim 10, wherein the series protection circuit further includes a resistor coupled in series between the JFET and parallel protection circuit.

13. The electronic device of claim 10, wherein the series protection circuit and parallel protection circuit are disposed within a single semiconductor package.

14. A method of protecting a semiconductor device from electrical overstress (EOS) and electro-static discharge (ESD) events, comprising:

providing a series protection circuit including,

a junction field-effect transistor (JFET), and

a resistor coupled in series with the JFET, wherein a conduction terminal of the JFET is coupled to a first terminal of the resistor and a gate terminal of the JFET is coupled to a second terminal of the resistor; and

providing a parallel protection circuit coupled to the gate terminal of the JFET.

15. The method of claim 14, wherein providing the parallel protection circuit includes providing a transient-voltage-suppression (TVS) diode.

16. The method of claim 14, wherein the parallel protection circuit is directly coupled to the gate terminal of the JFET.

17. The method of claim 14, further including disposing the series protection circuit and parallel protection circuit are within a single semiconductor package.

18. The method of claim 14, further including coupling the parallel protection circuit to a ground node.