Three-dimensional memory device including bottle-shaped memory stack structures and drain-select gate electrodes having cylindrical portions

• US 10,692,884 B2
• Filed: 09/21/2018
• Issued: 06/23/2020
• Est. Priority Date: 09/21/2018
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Cui, Zhixin, Sakakibara, Kiyohiko, Yada, Shinsuke
• Primary Examiner(s): Boulghassoul, Younes
• Application Number:
  US16/138,001
• Publication Number:
  US 20200098780A1
• Time in Patent Office: 641 Days
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, drain-select-level gate electrodes located over the alternating stack, memory openings extending through the alternating stack and a respective one of the drain-select-level gate electrodes, and memory opening fill structures located in the memory openings. The memory opening fill structures can have a stepped profile to provide a smaller lateral dimension at the level of the drain-select-level gate electrodes than within the alternating stack. Each of the drain-select-level gate electrodes includes a planar portion having two sets of vertical sidewall segments, and a set of cylindrical portions vertically protruding upward from the planar portion and laterally surrounding a respective one of the memory opening fill structures. The memory opening fill structures can be formed on-pitch as a two-dimensional array.

Claims

1. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

drain-select-level gate electrodes located over the alternating stack;

memory openings extending through the alternating stack and a respective one of the drain-select-level gate electrodes; and

memory opening fill structures located in the memory openings,

wherein each of the memory opening fill structures comprises a respective semiconductor channel;

wherein each semiconductor channel comprises;

a respective first vertically-extending portion extending through levels of the electrically conductive layers and having a first maximum lateral channel dimension, and

a respective second vertically-extending portion located at a level of the drain-select-level gate electrodes and having a second maximum lateral channel dimension that is less than the first maximum lateral channel dimension; and

wherein each of the drain-select-level gate electrodes comprises;

a planar portion having two sets of vertical sidewall segments; and

a set of cylindrical portions vertically protruding upward from the planar portion and laterally surrounding a respective one of the memory opening fill structures.

2. The three-dimensional memory device of claim 1, further comprising an isolation dielectric portion that includes:

a dielectric line portion laterally extending along a first horizontal direction, contacting sidewall segments of two planar portions of the drain-select-level gate electrodes, and sidewalls of two rows of cylindrical portions of the drain-select-level gate electrodes; and

a plurality of loop portions adjoined to sides of the dielectric line portion and overlying a respective cylindrical portion of two rows of cylindrical portions of the drain-select-level gate electrodes.

3. The three-dimensional memory device of claim 2, wherein each sidewall of the plurality of loop portions is vertically coincident with a sidewall of an underlying one of the plurality of cylindrical portions of the drain-select-level gate electrodes.

4. The three-dimensional memory device of claim 2, further comprising annular dielectric portions overlying additional cylindrical portions of the drain-select-level gate electrodes, wherein the annular dielectric portions comprise a same material as the isolation dielectric portion and are laterally spaced from the isolation dielectric portion.

5. The three-dimensional memory device of claim 1, wherein:

a first memory opening fill structure among the memory opening fill structures comprises a vertical axis passing through a geometrical center of the first memory opening fill structure; and

an inner sidewall of a most proximal one of the cylindrical portions of the drain-select-level gate electrodes is more proximal to the vertical axis than the electrically conducive layers are to the vertical axis.

6. The three-dimensional memory device of claim 5, wherein an outer sidewall of the most proximal one of the cylindrical portions of the drain-select-level gate electrodes is more proximal to the vertical axis than the electrically conductive layers are to the vertical axis.

7. The three-dimensional memory device of claim 1, wherein a lateral thickness of each of the cylindrical portions of the drain-select-level gate electrodes is the same as a vertical thickness of the planar portions of the drain-select-level gate electrodes.

8. The three-dimensional memory device of claim 1, wherein vertical sidewall segments within each set of vertical sidewall segments are adjoined to outer sidewalls of a row of cylindrical portions of one of the drain-select-level gate electrodes.

9. The three-dimensional memory device of claim 1, wherein each semiconductor channel comprises a respective annular portion having an outer periphery that is adjoined to an upper end of the respective first vertically-extending portion and an inner periphery that is adjoined to a lower end of the respective second vertically-extending portion.

10. The three-dimensional memory device of claim 9, wherein each semiconductor channel is laterally surrounded by a memory film that includes:

a first vertical memory film portion that contacts, and laterally surrounds, the respective first vertically-extending portion of one of the semiconductor channels;

a second vertical memory film portion that contacts, and laterally surrounds, the respective second vertically-extending portion of the one of the semiconductor channels; and

an annular memory film portion that contacts, and overlies, the annular portion of the one of the semiconductor channels.

11. The three-dimensional memory device of claim 10, wherein each of the first vertical memory film portion and the second vertical memory film portion comprises a respective portion of a blocking dielectric layer, a respective portion of a charge storage layer, and a respective portion of a tunneling dielectric layer.

12. The three-dimensional memory device of claim 10, wherein:

the first vertical memory film portion comprises a portion of a blocking dielectric layer, a portion of a charge storage layer, and a portion of a tunneling dielectric layer; and

the annular memory film portion comprises another portion of the blocking dielectric layer in direct contact with another portion of the tunneling dielectric layer.

13. The three-dimensional memory device of claim 1, wherein each of the memory opening fill structures further comprises an encapsulated cavity that vertically extends through each level of the electrically conductive layers.

14. The three-dimensional memory device of claim 13, wherein:

each of the memory opening fill structures comprises a dielectric core;

the dielectric core includes a closed inner surface that defines an entire volume of the encapsulated cavity; and

the dielectric core includes a neck portion located above the encapsulated cavity and protrudes through a respective one of the drain-select-level gate electrodes.