Oxide semiconductor, thin film transistor, and display device

• US 10,692,894 B2
• Filed: 10/16/2018
• Issued: 06/23/2020
• Est. Priority Date: 10/24/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ito, Shunichi, Sasaki, Toshinari, Hosoba, Miyuki, Sakata, Junichiro
• Primary Examiner(s): McCall-Shepard, Sonya D.
• Application Number:
  US16/161,573
• Publication Number:
  US 20190051673A1
• Time in Patent Office: 616 Days
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to control composition and a defect of an oxide semiconductor, another object is to increase a field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with a reduced off current. A solution is to employ an oxide semiconductor whose composition is represented by InMO₃(ZnO)_m, where M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al, and m is preferably a non-integer number of greater than 0 and less than 1. The concentration of Zn is lower than the concentrations of In and M. The oxide semiconductor has an amorphous structure. Oxide and nitride layers can be provided to prevent pollution and degradation of the oxide semiconductor.

Claims

1. A semiconductor device comprising:

a pixel portion comprising a transistor,

the transistor comprising;

a gate;

a first insulating layer over the gate;

a second insulating layer over and in contact with the first insulating layer;

a semiconductor layer over and in contact with the second insulating layer;

a third insulating layer over and in contact with the semiconductor layer;

a fourth insulating layer over and in contact with the third insulating layer; and

a source and a drain each electrically connected to the semiconductor layer; and

a display element comprising;

a first electrode electrically connected to one of the source and the drain through a contact hole in the third insulating layer; and

a second electrode over the first electrode,

wherein;

the semiconductor layer includes an oxide semiconductor containing In, Ga, and Zn,

the second insulating layer and the third insulating layer each contain silicon and oxygen,

the first insulating layer and the fourth insulating layer each contain silicon and nitrogen, and

in a channel length direction of the transistor, the second insulating layer and the third insulating layer are in contact with each other with the semiconductor layer therebetween.

2. The semiconductor device according to claim 1, wherein the display element further comprises a liquid crystal layer between the first and second electrodes.

3. The semiconductor device according to claim 1, wherein the gate comprises a first layer containing Ti, and a second layer containing Cu over the first layer.

4. The semiconductor device according to claim 1, wherein the gate comprises a first layer containing Mo, and a second layer containing Cu over the first layer.

5. The semiconductor device according to claim 1, wherein the source and the drain each comprise a layer containing Cu.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor includes nanocrystals.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor is a non-single-crystal semiconductor.

8. A semiconductor device comprising:

a pixel portion comprising a transistor,

the transistor comprising;

a gate;

a first insulating layer over the gate;

a second insulating layer over and in contact with the first insulating layer;

a semiconductor layer over and in contact with the second insulating layer;

a third insulating layer over and in contact with the semiconductor layer;

a fourth insulating layer over and in contact with the third insulating layer; and

a source and a drain each electrically connected to the semiconductor layer; and

a display element comprising;

a first electrode electrically connected to one of the source and the drain through a contact hole in the third insulating layer; and

a second electrode over the first electrode,

wherein;

the semiconductor layer includes an oxide semiconductor containing In, Ga, and Zn,

the second insulating layer and the third insulating layer each contain silicon and oxygen,

the first insulating layer and the fourth insulating layer each contain silicon and nitrogen, and

in a channel length direction of the transistor, the semiconductor layer is surrounded by the second insulating layer and the third insulating layer.

9. The semiconductor device according to claim 8, wherein the display element further comprises a liquid crystal layer between the first and second electrodes.

10. The semiconductor device according to claim 8, wherein the gate comprises a first layer containing Ti, and a second layer containing Cu over the first layer.

11. The semiconductor device according to claim 8, wherein the gate comprises a first layer containing Mo, and a second layer containing Cu over the first layer.

12. The semiconductor device according to claim 8, wherein the source and the drain each comprise a layer containing Cu.

13. The semiconductor device according to claim 8, wherein the oxide semiconductor includes nanocrystals.

14. The semiconductor device according to claim 8, wherein the oxide semiconductor is a non-single-crystal semiconductor.