Semiconductor device

• US 10,693,001 B2
• Filed: 11/17/2017
• Issued: 06/23/2020
• Est. Priority Date: 12/25/2008
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki, Nakamura, Ryota
• Primary Examiner(s): Erdem, Fazli
• Application Number:
  US15/816,481
• Publication Number:
  US 20180076317A1
• Time in Patent Office: 949 Days
• Field of Search: 257 77
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/0485 Ohmic electrodes
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.

Claims

1. A semiconductor device, comprising:

a semiconductor layer made of SiC, the semiconductor layer having a front surface and a back surface;

a gate trench formed in a surface portion of the semiconductor layer;

a gate insulating film formed on an inner surface of the gate trench;

a gate electrode embedded in the gate trench and on the gate insulating film;

a body region of a second conductivity type formed in the semiconductor layer and defining one part of a side surface of the gate trench;

a source region of a first conductivity type formed on a front surface side of the body region in the semiconductor layer;

a source trench penetrating the source region from the front surface of the semiconductor layer;

a gate pad formed over a part of the semiconductor layer; and

a source conductive member covering most of the semiconductor device except the gate pad in a plan view, wherein

the source conductive member is in contact with the gate insulating film, the source region and an inner surface of the source trench,

the source conductive member includes a first layer and a second layer on the first layer such that an interface between the first layer and the second layer is positioned both inside and outside the source trench,

the body region includes a body contact region formed on a side surface of the source trench,

the source conductive member is in contact with the body contact region in the source trench,

the body contact region is covered with the source region from the front surface side of the semiconductor layer, and

the body contact region is not exposed from the front surface of the semiconductor layer.

2. The semiconductor device according to claim 1, wherein the source trench has a depth that is deeper than a depth of the gate trench.

3. The semiconductor device according to claim 1, further comprising a drain electrode formed on the back surface of the semiconductor layer.

4. The semiconductor device according to claim 3, wherein the drain electrode has a multilayer structure.

5. The semiconductor device according to claim 1, further comprising a second conductivity type layer formed in a bottom portion of the gate trench in the semiconductor layer.

6. The semiconductor device according to claim 1, wherein the source trench has a width that is greater than a width of the gate trench.

7. The semiconductor device according to claim 1, further comprising an insulating film covering the gate electrode such that the insulating film is protruded upward from the front surface of the semiconductor layer.

8. The semiconductor device according to claim 4, wherein the multilayer structure includes:

a polysilicon layer in a portion of the multilayer structure in contact with the semiconductor layer, and a metal layer on the polysilicon layer.

9. The semiconductor device according to claim 8, wherein an intermediate layer is interposed between the polysilicon layer and the metal layer.

10. The semiconductor device according to claim 9, wherein

the metal layer has a layer containing Al, and

the intermediate layer has a structure obtained by laminating a Ti layer and then a TiN layer from a side of the polysilicon layer.

11. The semiconductor device according to claim 1, wherein

the gate insulating film has a bottom portion located on a bottom surface of the gate trench and a side portion located on the side surface of the gate trench, and

a thickness of the bottom portion and a thickness of the side portion are different from each other.

12. The semiconductor device according to claim 11,

wherein the thickness of the bottom portion of the gate insulating film is less than the thickness of the side portion of the gate insulating film.

13. The semiconductor device according to claim 12, wherein the thickness of the bottom portion of the gate insulating film is 150 to 500 Å

.

14. The semiconductor device according to claim 12, wherein the thickness of the side portion of the gate insulating film is 300 to 1000 Å

.

15. The semiconductor device according to claim 1, wherein the source conductive member has a multilayer structure.

16. The semiconductor device according to claim 15, wherein the multilayer structure includes:

a polysilicon layer in a portion of the multilayer structure in contact with the semiconductor layer, and a metal layer on the polysilicon layer.

17. The semiconductor device according to claim 16, wherein an intermediate layer is interposed between the polysilicon layer and the metal layer.

18. The semiconductor device according to claim 17, wherein the intermediate layer protrudes from an inner portion of the source trench to a height higher than a surface of the source region in a vertical direction.

19. The semiconductor device according to claim 18, wherein the intermediate layer includes Ti.

20. The semiconductor device according to claim 5, wherein the second conductivity type layer is disposed to be spaced inward from the side surface of the gate trench.

21. The semiconductor device according to claim 17, wherein the intermediate layer has a first curved portion and a second curved portion disposed over the first curved portion.

22. The semiconductor device according claim 21, further comprising an insulating film covering the gate electrode such that the insulating film is protruded upward from the front surface of the semiconductor layer, wherein

the intermediate layer has a connecting portion disposed at a level between an upper surface of the insulating film and a lower surface of the insulating film in a thickness direction of the insulating film, where the first curved portion is connected to the second curved portion.