Interlayer dielectric for non-planar transistors
First Claim
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1. An integrated circuit (IC) structure, comprising:
- a fin having a source and a drain;
a transistor gate formed on the fin between the source and the drain, wherein the transistor gate comprises a gate electrode, a gate dielectric between the gate electrode and the fin, and a pair of sidewalls formed on opposing sides of the gate electrode;
a capping structure over the gate electrode;
spacers on the pair of sidewalls;
an adhesion liner contacting the spacers; and
a dielectric layer contacting the adhesion liner, wherein an upper portion of the dielectric layer has a higher density than a lower portion of the dielectric layer, wherein both the densified portion of the dielectric layer and a non-densified portion of the dielectric layer contact the adhesion liner.
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Abstract
The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.
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Citations
20 Claims
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1. An integrated circuit (IC) structure, comprising:
- a fin having a source and a drain;
a transistor gate formed on the fin between the source and the drain, wherein the transistor gate comprises a gate electrode, a gate dielectric between the gate electrode and the fin, and a pair of sidewalls formed on opposing sides of the gate electrode;
a capping structure over the gate electrode;
spacers on the pair of sidewalls;
an adhesion liner contacting the spacers; and
a dielectric layer contacting the adhesion liner, wherein an upper portion of the dielectric layer has a higher density than a lower portion of the dielectric layer, wherein both the densified portion of the dielectric layer and a non-densified portion of the dielectric layer contact the adhesion liner. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
- a fin having a source and a drain;
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13. A method of forming an integrated circuit (IC) structure, comprising:
- forming a fin;
forming a source and a drain in the fin;
forming a transistor gate on the fin between the source and the drain, wherein the transistor gate comprises a gate electrode, a gate dielectric between the gate electrode and the fin, and a pair of sidewalls formed on opposing sides of the gate electrode;
forming a capping structure over the gate electrode;
forming spacers on the pair of sidewalls;
forming an adhesion liner contacting the spacers;
forming a dielectric layer contacting the adhesion liner; and
forming a densified portion of the dielectric layer resulting in a densified portion of the dielectric layer and a non-densified portion of the dielectric layer, wherein both the densified portion of the dielectric layer and a non-densified portion of the dielectric layer contact the adhesion liner. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
- forming a fin;
Specification