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Interlayer dielectric for non-planar transistors

  • US 10,693,006 B2
  • Filed: 07/19/2018
  • Issued: 06/23/2020
  • Est. Priority Date: 12/06/2011
  • Status: Active Grant
First Claim
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1. An integrated circuit (IC) structure, comprising:

  • a fin having a source and a drain;

    a transistor gate formed on the fin between the source and the drain, wherein the transistor gate comprises a gate electrode, a gate dielectric between the gate electrode and the fin, and a pair of sidewalls formed on opposing sides of the gate electrode;

    a capping structure over the gate electrode;

    spacers on the pair of sidewalls;

    an adhesion liner contacting the spacers; and

    a dielectric layer contacting the adhesion liner, wherein an upper portion of the dielectric layer has a higher density than a lower portion of the dielectric layer, wherein both the densified portion of the dielectric layer and a non-densified portion of the dielectric layer contact the adhesion liner.

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