Structure of S/D contact and method of making same

• US 10,693,009 B2
• Filed: 02/04/2019
• Issued: 06/23/2020
• Est. Priority Date: 08/15/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Yu-Lien, Lee, Tung Ying, Fan, Chun-Hsiang
• Primary Examiner(s): Smith, Bradley
• Assistant Examiner(s): Goodwin, David J
• Application Number:
  US16/266,454
• Publication Number:
  US 20190181267A1
• Time in Patent Office: 505 Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A semiconductor device includes a fin feature in a substrate, a stack of semiconductor layers over the fin feature. Each of the semiconductor layers does not contact each other. The device also includes a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers. A surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers. The device also includes a conductive material layer encircling each of the semiconductor layers and filling in spaces between each of two semiconductor layers.

Claims

1. A method comprising:

forming a first fin structure on a substrate;

forming a first semiconductor layer over the first fin structure;

forming a second semiconductor layer over the first semiconductor layer, the second semiconductor layer being formed of a different material than the first semiconductor layer;

forming a third semiconductor layer over the first fin structure, the third semiconductor layer being formed of the same material as the first semiconductor layer and physically contacting the first fin structure;

performing a treatment process on the first semiconductor layer, wherein the performing of treatment process on the first semiconductor layer includes performing the treatment process on the third semiconductor layer;

removing the treated first semiconductor layer, wherein after the removing of the treated first semiconductor layer, the treated third semiconductor layer is still disposed over the first fin structure; and

forming a conductive material on the second semiconductor layer after the removing of the treated first semiconductor layer.

2. The method of claim 1, wherein the second semiconductor layer is part of a source/drain feature.

3. The method of claim 1, further comprising:

forming a gate stack including a first gate electrode over the first fin structure; and

removing the first gate electrode from the gate stack after performing the treatment process on the first semiconductor layer and prior to removing the treated first semiconductor layer.

4. The method of claim 1, wherein the performing of the treatment process on the first semiconductor layer includes performing an annealing process to oxidize the first semiconductor layer.

5. The method of claim 1, further comprising forming a fourth semiconductor layer over the second semiconductor layer, the fourth semiconductor layer being formed of the same material as the first semiconductor layer, and

wherein the performing of treatment process on the first semiconductor layer includes performing the treatment process on the fourth semiconductor layer, and

wherein the removing of the treated first semiconductor layer includes removing the treated fourth semiconductor layer.

6. The method of claim 1, further comprising forming a third semiconductor layer over the first fin structure, the third semiconductor layer being formed of the same material as the first semiconductor layer and physically contacting the first fin structure,

wherein the performing of treatment process on the first semiconductor layer includes performing the treatment process on the third semiconductor layer, and

wherein after the removing of the treated first semiconductor layer, the treated third semiconductor layer is still disposed over the first fin structure.

7. The method of claim 1, further comprising:

forming a second fin structure over on the substrate;

wherein the forming of the first semiconductor layer over the first fin structure includes forming the first semiconductor layer over the second fin structure,

wherein the forming of the second semiconductor layer over the first semiconductor layer includes forming the second semiconductor layer over the second fin structure, and

wherein the conductive material extends from the second semiconductor layer over the first fin structure to the second semiconductor layer over the second fin structure.

8. The method of claim 1, wherein the performing of the treatment process on the first semiconductor layer includes oxidizing the first semiconductor layer;

wherein removing the treated first semiconductor layer includes removing the oxidized first semiconductor layer to expose a bottom surface of the second semiconductor layer, the bottom surface of the second semiconductor layer facing the substrate, and

wherein forming the conductive material on the second semiconductor layer includes forming the conductive material directly on the bottom surface of second semiconductor layer.

9. The method of claim 1, wherein the conductive material includes a metal material.

10. A method comprising:

forming a fin structure on a substrate, the fin structure having a gate region and source/drain region;

forming a gate structure over the gate region of the fin structure;

forming a first semiconductor layer over the source/drain region of the fin structure;

forming a second semiconductor layer over the first semiconductor layer in the source/drain region of the fin structure, the second semiconductor layer being formed of a different material than the first semiconductor layer;

forming a third semiconductor layer over the second semiconductor layer in the source/drain region of the fin structure, the third semiconductor layer being formed of the same material as the first semiconductor layer;

oxidizing the first and third semiconductor layers;

removing the oxidized third semiconductor layer; and

forming a conductive material on the second semiconductor layer after the removing of the oxidized third semiconductor layer.

11. The method of claim 10, further comprising recessing the fin structure in the source/drain region prior to forming the first semiconductor layer over the fin structure in the source/drain region.

12. The method of claim 10, wherein the removing of the oxidized third semiconductor layer includes removing the oxidized first semiconductor layer.

13. The method of claim 10, wherein the oxidized first semiconductor layer is positioned under the second semiconductor layer while the forming of the conductive material on the second semiconductor layer occurs.

14. The method of claim 10, further comprising forming a fourth semiconductor layer over the third semiconductor layer in the source/drain region of the fin structure, the fourth semiconductor layer being formed of the same material as the second semiconductor layer, and

wherein the forming of the conductive material on the second semiconductor layer after the removing of the oxidized third semiconductor layer includes forming the conductive material on the fourth semiconductor layer such that the conductive material extends continuously form the second semiconductor layer to the fourth semiconductor layer.

15. The method of claim 10, further comprising forming a shallow trench isolation structure within the substrate, and

wherein the forming of the conductive material on the second semiconductor layer includes forming the conductive material directly on the second semiconductor layer and the shallow trench isolation structure.

16. The method of claim 10, wherein the first semiconductor layer includes SiGe and the second semiconductor layer includes Si.

17. The method of claim 10, wherein the gate structure includes a polysilicon gate electrode, the method further comprising:

removing the polysilicon gate electrode from the gate structure to form a trench after oxidizing the first and third semiconductor layers; and

forming a metal gate electrode in the trench prior to removing the oxidized third semiconductor layer.

18. A method for fabricating a semiconductor device, the method comprising:

receiving a substrate, the substrate including;

a fin feature formed by a portion of the silicon substrate;

isolation regions between each of the fin feature;

a dummy gate stack in a portion of the fin feature; and

a gate spacer along sidewalls of the dummy gate stack;

recessing portions of the fin feature, beside the dummy gate stack, to form a source/drain (S/D) trench;

forming pre-S/D stack in the S/D trench, wherein the pre-S/D stack including one or more pairs of a first semiconductor layer and a second semiconductor layer;

applying an annealing process to convert the first semiconductor layer to a semiconductor oxide layer;

forming an interlayer dielectric ILD layer over the substrate;

replacing the dummy gate with a high-k/metal gate (HK/MG);

forming a contact opening to expose a portion of the pre-S/D stack, including the semiconductor oxide layer;

selectively removing the exposed semiconductor oxide layer to form a space between each of the first semiconductor layer; and

filling in the contact opening with a metal layer, including filling in the space between each of the first semiconductor layer.

19. The method of claim 18, wherein forming the contact opening includes:

etching the ILD layer through a patterned hard mask and extending to etch the isolation region that a top surface of the recessed isolation region is same or above a top surface of the semiconductor oxide layer at a bottom of the pre-S/D stack.

20. The method of claim 19, wherein the semiconductor oxide layer at the bottom of the pre-S/D stack remain intact during selective removing the other semiconductor oxide layer.

21. The method of claim 18, further comprising:

more than one pre-S/D stacks are exposed in the contact opening; and

filling in the contact opening with the metal layer, including filling in a space between each of pre-S/D stacks with in the contact opening.